ZHCSJX1B NOVEMBER 2008 – June 2019 TPS40197
PRODUCTION DATA.
The TPS40197 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is prebiased. When the soft start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous rectification by starting the first LDRV pulse with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensures that the output voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of switching until the low-side MOSFET is turned on for the full (1-D) interval is defined by 32 clock cycles.