ZHCSJX1B NOVEMBER   2008  – June 2019 TPS40197

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Package Dissipation Ratings
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable
      2. 8.3.2  Oscillator
      3. 8.3.3  UVLO
      4. 8.3.4  Start-up Sequence and Timing
      5. 8.3.5  Selecting the Short Circuit Current
      6. 8.3.6  Voltage Reference and Dynamic VID
      7. 8.3.7  Minimum On-Time Consideration
      8. 8.3.8  BP Regulator
      9. 8.3.9  Prebias Start-up
      10. 8.3.10 Drivers
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 第三方产品免责声明
    2. 10.2 文档支持
      1. 10.2.1 相关器件
      2. 10.2.2 相关文档
    3. 10.3 接收文档更新通知
    4. 10.4 社区资源
    5. 10.5 商标
    6. 10.6 静电放电警告
    7. 10.7 Glossary
  11. 11机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.6 Voltage Reference and Dynamic VID

To provide optimized voltage for Smart-Reflex™ DSP cores, the TPS40197 is designed to monitor the VID code at all times once soft-start is complete, and actively adjusts its output voltage if the VID code should change during normal operation. A digital-to-analog converter (DAC) generates a reference voltage based on the state of logical signals at pins VID0 through VID3. The DAC decodes the 4-bit logic signal into one of the discrete voltages shown in Table 2. The default setting for the output is 1.2 V (VID code 1111). The output voltage is 1.2 V during initial start or restart after cycling the input, toggling EN pin or recovering from a short circuit at the output.

To ensure that no erroneous output voltage is produced, the TPS40197 VID inputs have internal anti-skew circuit with approximately 550 ns of filtering time. Each VID input is pulled up to an internal 1.68-V source with 80-μA pullup current for use with open-drain outputs.

The output voltage can be programmed from 0.9 V to 1.2 V in 20 mV steps. Smooth upward and downward core voltage transition can be achieved by programming the transition rate with an external capacitor connected from REF pin to GND. The required capacitance can be calculated using Equation 5.

Equation 5. TPS40197 q_cref_lus853.gif

where

  • VVID-TR is the total voltage transition through VID
  • IREF is the internal reference source/sink current
  • TTR is the intended total VID voltage transition time

CREF must be limited to a maximum of 1.5 μF to avoid interfering with the soft start. A capacitor (CREF) with a minimum capacitance of 100-nF is also recommended.

Table 2. Voltage Identification Codes

VID TERMINALS (0 = LOW, 1 = HIGH) VREF
VID3 VID2 VID1 VID0 (Vdc)
0 0 0 0 0.90
0 0 0 1 0.92
0 0 1 0 0.94
0 0 1 1 0.96
0 1 0 0 0.98
0 1 0 1 1.00
0 1 1 0 1.02
0 1 1 1 1.04
1 0 0 0 1.06
1 0 0 1 1.08
1 0 1 0 1.10
1 0 1 1 1.12
1 1 0 0 1.14
1 1 0 1 1.16
1 1 1 0 1.18
1 1 1 1 1.20