ZHCSJX1B NOVEMBER   2008  – June 2019 TPS40197

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Package Dissipation Ratings
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable
      2. 8.3.2  Oscillator
      3. 8.3.3  UVLO
      4. 8.3.4  Start-up Sequence and Timing
      5. 8.3.5  Selecting the Short Circuit Current
      6. 8.3.6  Voltage Reference and Dynamic VID
      7. 8.3.7  Minimum On-Time Consideration
      8. 8.3.8  BP Regulator
      9. 8.3.9  Prebias Start-up
      10. 8.3.10 Drivers
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 第三方产品免责声明
    2. 10.2 文档支持
      1. 10.2.1 相关器件
      2. 10.2.2 相关文档
    3. 10.3 接收文档更新通知
    4. 10.4 社区资源
    5. 10.5 商标
    6. 10.6 静电放电警告
    7. 10.7 Glossary
  11. 11机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ 85°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE AND VID
VFB FB input voltage 0.9 V ≤ VVID ≤ 1.2 V, 0°C ≤ TJ ≤ 85°C –0.5% 0.5% VVID
0.9 V ≤ VVID ≤ 1.2 V, –40°C ≤ TJ ≤ 85°C –1.0% 1.0%
IVID VID pullup current 50 80 120 μA
VVID VID pullup voltage 1.60 1.68 1.78 V
tANTI-SKEW(1) Anti-skew filtering time 300 550 750 ns
VVIDH VID high-level input voltage 0.8 1.0 1.3 V
VVIDL VID low-level input voltage 0.30 0.55 0.70 V
IREF REF source/sink current 400 650 850 μA
INPUT SUPPLY
VVDD Normal input supply voltage range 4.5 14.0 V
IVDD Operating current VENABLE = 3 V 2.5 4.5 mA
VENABLE = 0.6 V 45 70 μA
SOFT START
tSS Soft-start time 3.3 5.5 7 ms
tSSDLY Soft-start delay time 1.3 2.3 4
tREG Time to regulation 5.0 8.0 11
ON-BOARD REGULATOR
VBP Output voltage VVDD > 6 V, IBP ≤ 10 mA 5.1 5.3 5.5 V
VDO Regulator dropout voltage (VVDD–VBP) VVDD > 5 V, IBP ≤ 25 mA 350 550 mV
ISC Regulator current limit threshold 50 mA
IBP Average current 50
OSCILLATOR
fSW Switching frequency 420 520 600 kHz
VRAMP(1) Ramp amplitude 1 V
PWM
DMAX(1) Maximum duty cycle 85%
tON(min)(1) Minimum controllable pulse 110 ns
tDEAD Output driver dead time HDRV off to LDRV on 50
LDRV off to HDRV on 25
ERROR AMPLIFIER
GBWP(1) Gain bandwidth product 7 10 MHz
AOL(1) Open loop gain 60 dB
IIB Input bias current (current out of FB pin) 100 nA
IEAOP Output source current VFB = 0 V 1 mA
IEAOM Output sink current VFB = 2 V 1
UNDERVOLTAGE LOCKOUT
VUVLO Turn-on voltage 3.9 4.2 4.4 V
UVLOHYST Hysteresis 700 850 1000 mV
SHUTDOWN
VIH High-level input voltage, ENABLE 1.9 3 V
VIL Low-level input voltage, ENABLE 0.6 1.2
OUTPUT DRIVERS
RHDHI High-side driver pull-up resistance (VBOOT – VSW ) - 4.5 V, IHDRV = – 100 mA 3 6 Ω
RHDLO High-side driver pull-down resistance (VBOOT – VSW ) - 4.5 V, IHDRV = 100 mA 1.5 3
RLDHI Low-side driver pull-up resistance ILDRV = –100 mA 2.5 5
RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 0.8 1.5
tHRISE(1) High-side driver rise time CLOAD = 1 nF 15 35 ns
tHFALL(1) High-side driver fall time 10 25
tLRISE(1) Low-side driver rise time 15 35
tLFALL(1) Low-side driver fall time 10 25
SHORT CIRCUIT PROTECTION
tPSS(min)(1) Minimum pulse time during short circuit 250 ns
tBLNK(1) Switch leading-edge blanking pulse time 60 90 120
tOFF Off-time between restart attempts 30 50 ms
VILIM Short circuit comparator threshold voltage RCOMP(GND) = OPEN, TJ = 25°C 160 200 240 mV
RCOMP(GND) = 4 kΩ, TJ = 25°C 80 100 120
RCOMP(GND) = 12 kΩ, TJ = 25°C 228 280 342
VILIMH Short circuit threshold voltage on high-side MOSFET TJ = 25°C 400 550 650
POWER GOOD
VOV Feedback voltage limit for powergood 106% 110% 114% VID
VUV 86% 90% 94%
VPG_HYST Powergood hysteresis voltage at FB pin 10 30 70 mV
RPGD Pull-down resistance of PGD pin VFB < 90% VVID mV or VFB > 110% VVID 7 50 Ω
IPDGLK Leakage current 90% VVID ≤ VFB ≤ 100% VVID, VPGOOD = 5 V 7 12 μA
BOOT DIODE
VDFWD IBOOT = 5 mA 0.5 0.8 1.2 V
THERMAL SHUTDOWN
TJSD(1) Junction shutdown temperature 140 °C
TJSDH(1) Hysteresis 20
(1) Specified by design. Not production tested.