ZHCSP87A December   2022  – September 2023 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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7.16 I2C Requirements and Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. VDD = I2C pullup voltage (3.3 V or 1.8 V)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I2C_IRQ1s, I2C_IRQ2
I2C_IRQ1m
SDA and SCL Characteristics (Standard, Fast, Fast-mode Plus)
VIL Input low signal 0.54 V
VIH Input high signal 1.3 V
VDD = 3.3 V INPUT LOGIC THRESHOLDS
VIL Input low signal 0.9 V
VIH Input high signal 2.31 V
VHYS Input hysteresis 0.165 V
VOL Output low voltage VDD = 1.8V, IOL=2 mA 0.36
VOL Output low voltage VDD = 3.3V, IOL=3 mA 0.4 V
IOL Max output low current VOL=0.4 V 12 mA
ILEAK Input leakage current Voltage on pin = 3.3V –5 5 µA
CI pin capacitance (internal) 10 pF
Cb Capacitive load for each bus line (external). Applies in Standard-mode and Fast-mode. 400 pF
Cb Capacitive load for each bus line (external).  Applies in Fast-mode Plus. 550 pF
COMMON TIMING
tSP I2C pulse width suppressed 50 ns
SDA and SCL Characteristics (Standard Mode)
fSCLS Clock frequency (slave) VDD = 1.8V or 3.3V 100 kHz
tHD;STA Start or repeated start condition hold time VDD = 1.8V or 3.3V 4 µs
tLOW SCL Clock low time VDD = 1.8V or 3.3V 4.7 µs
tHIGH SCL Clock high time VDD = 1.8V or 3.3V 4 µs
tSU;STA Start or repeated start condition setup time VDD = 1.8V or 3.3V 4.7 µs
tHD;DAT Serial data hold time (1) VDD = 1.8V or 3.3V 0 (2) - (3) ns
tSU;DAT Serial data setup time VDD = 1.8V or 3.3V 250 ns
tr Rise time of SCL and SDA signals VDD = 1.8V or 3.3V; RPU = 2.8 kΩ; Cb = 400pF; measure 0.3 × VDD to 0.7 × VDD 1000 ns
tof Output fall time from VIH(MIN) to VIL(MAX) VDD = 1.8V or 3.3V; measure 0.3 × VDD to 0.7 × VDD 250 (4) ns
tf Fall time of SCL and SDA signals (2) (4) (5) VDD = 1.8V, RPU = 2.8 kΩ; 10 pF ≤ Cb ≤ 400 pF 300 ns
tf Fall time of SCL and SDA signals (2) (4) (5) VDD = 3.3V, RPU = 2.8 kΩ; 10 pF ≤ Cb ≤ 400 pF 300 ns
tSU;STO Stop condition setup time VDD = 1.8V or 3.3V 4 µs
tBUF Bus free time between stop and start VDD = 1.8V or 3.3V 4.7 µs
tVD;DAT Valid data time (6) Transmitting Data; VDD = 1.8V or 3.3V, SCL low to SDA output valid 3.45 (3) µs
tVD;ACK Valid data time of ACK condition Transmitting Data; VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA valid 3.45 (3) µs
SDA and SCL Characteristics (Fast Mode)
fSCLS Clock frequency (slave) VDD = 1.8V or 3.3V 400 kHz
tHD;STA Start or repeated start condition hold time VDD = 1.8V or 3.3V 0.6 µs
tLOW SCL Clock low time VDD = 1.8V or 3.3V 1.3 µs
tHIGH SCL Clock high time VDD = 1.8V or 3.3V 0.6 µs
tSU;STA Start or repeated start condition setup time VDD = 1.8V or 3.3V 0.6 µs
tHD;DAT Serial data hold time (1) VDD = 1.8V or 3.3V 0 (2) - (3) ns
tSU;DAT Serial data setup time VDD = 1.8V or 3.3V 100 (7) ns
tr Rise time of SCL and SDA signals VDD = 1.8V or 3.3V; RPU = 850 Ω; Cb = 400 pF; measure 0.3 × VDD to 0.7 × VDD 20 300 ns
tof Output fall time from VIH(MIN) to VIL(MAX) VDD = 1.8V; measure 0.3 × VDD to 0.7 × VDD 6.55 250 (4) ns
tof Output fall time from VIH(MIN) to VIL(MAX) VDD = 3.3V; measure 0.3 × VDD to 0.7 × VDD 12 250 (4) ns
tf Fall time of SCL and SDA signals (2) (4) (5) VDD = 1.8V; RPU = 850 Ω; 10 pF ≤ Cb ≤ 400 pF 6.55 300 ns
tf Fall time of SCL and SDA signals (2) (4) (5) VDD = 3.3V; RPU = 850 Ω; 10 pF ≤ Cb ≤ 400 pF 12 300 ns
tSU;STO Stop condition setup time VDD = 1.8V or 3.3V 0.6 µs
tBUF Bus free time between stop and start VDD = 1.8V or 3.3V 1.3 µs
tVD;DAT Valid data time (6) Transmitting Data; VDD = 1.8V or 3.3V, SCL low to SDA output valid 0.9 (3) µs
tVD;ACK Valid data time of ACK condition Transmitting Data; VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low 0.9 (3) µs
(1) tHD;DAT = the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
(3) The maximum tHD;DAT could be 3.45 µs and 0.9 µs for Standard-mode and Fast-mode, but must be less than the maximum tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the setup time before it releases the clock.
(4) The maximum tf for the SDA and SCL bus lines is stated in these tables as 300 ns is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (RS) to be connected between the SDA and SCL pins and the SDA and SCL bus lines without exceeding the maximum specified tf.
(5) In Fast-mode Plus, fall time is specified the same for both ouput stage and bus timing. If series resistors (RS) are used, designers should allow for this when considering bus timing.
(6) tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
(7) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.