SLVSJG7 May   2026 TPS25751A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
      1. 6.1.1 TPS25751AD and TPS25751AS - Absolute Maximum Ratings
      2. 6.1.2 TPS25751AD - Absolute Maximum Ratings
      3. 6.1.3 TPS25751AS - Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
      1. 6.3.1 TPS25751AD - Recommended Operating Conditions
      2. 6.3.2 TPS25751AS - Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
      1. 6.5.1 TPS25751AD - Thermal Information
      2. 6.5.2 Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PP_5V Power Switch Characteristics
    9. 6.9  PPHV Power Switch Characteristics - TPS25751AD
    10. 6.10 PP_EXT Characteristics - TPS25751AS
    11. 6.11 Power Path Supervisory
    12. 6.12 CC Cable Detection Parameters
    13. 6.13 CC VCONN Parameters
    14. 6.14 CC PHY Parameters
    15. 6.15 Thermal Shutdown Characteristics
    16. 6.16 ADC Characteristics
    17. 6.17 Input/Output (I/O) Characteristics
    18. 6.18 BC1.2 Characteristics
    19. 6.19 I2C Requirements and Characteristics
    20. 6.20 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
        6. 8.3.1.6 Squelch Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
      3. 8.3.3  Power Paths
        1. 8.3.3.1 Internal Sourcing Power Paths
          1. 8.3.3.1.1 PP_5V Current Clamping
          2. 8.3.3.1.2 PP_5V Local Overtemperature Shut Down (OTSD)
          3. 8.3.3.1.3 PP_5V OVP
          4. 8.3.3.1.4 PP_5V UVLO
          5. 8.3.3.1.5 PP_5V Reverse Current Protection
          6. 8.3.3.1.6 PP_CABLE Current Clamp
          7. 8.3.3.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)
          8. 8.3.3.1.8 PP_CABLE UVLO
        2. 8.3.3.2 TPS25751AD Internal Powerpath
          1. 8.3.3.2.1 Overvoltage Protection (OVP)
          2. 8.3.3.2.2 Reverse-Current Protection (RCP)
          3. 8.3.3.2.3 VBUS UVLO
          4. 8.3.3.2.4 Discharging VBUS to Safe Voltage
        3. 8.3.3.3 External Powerpath Control PP_EXT
          1. 8.3.3.3.1 Overvoltage Protection (OVP)
          2. 8.3.3.3.2 Reverse-Current Protection (RCP)
          3. 8.3.3.3.3 VBUS UVLO
          4. 8.3.3.3.4 Discharging VBUS to Safe Voltage
      4. 8.3.4  Cable Plug and Orientation Detection
        1. 8.3.4.1 Configured as a Source
        2. 8.3.4.2 Configured as a Sink
        3. 8.3.4.3 Configured as a DRP
        4. 8.3.4.4 Dead Battery Advertisement
      5. 8.3.5  Overvoltage Protection (CC1, CC2)
      6. 8.3.6  Default Behavior Configuration (ADCIN1, ADCIN2)
      7. 8.3.7  ADC
      8. 8.3.8  Liquid Detection
      9. 8.3.9  BC 1.2 (USB_P, USB_N)
      10. 8.3.10 Digital Interfaces
        1. 8.3.10.1 General GPIO
        2. 8.3.10.2 I2C Interface
          1. 8.3.10.2.1 I2C Interface Description
            1. 8.3.10.2.1.1 I2C Clock Stretching
            2. 8.3.10.2.1.2 I2C Address Setting
            3. 8.3.10.2.1.3 Unique Address Interface
            4. 8.3.10.2.1.4 Pin Strapping to Configure Default Behavior
      11. 8.3.11 Digital Core
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power States
      2. 8.4.2 Schottky for Current Surge Protection
      3. 8.4.3 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Liquid Detection Design Requirements
        2. 9.2.1.2 BC1.2 Application Design Requirements
        3. 9.2.1.3 USB Data Support Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Liquid Detection
        2. 9.2.2.2 BC1.2 Application
        3. 9.2.2.3 USB Data Support
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Liquid Detection Application Curves
        2. 9.2.3.2 BC1.2 Application Curves
        3. 9.2.3.3 USB Data Support Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 3.3V Power
        1. 9.3.1.1 VIN_3V3 Input Switch
      2. 9.3.2 1.5V Power
      3. 9.3.3 Recommended Supply Load Capacitance
    4. 9.4 Layout
      1. 9.4.1 TPS25751AD - Layout
        1. 9.4.1.1 Layout Guidelines
          1. 9.4.1.1.1 Recommended Via Size
          2. 9.4.1.1.2 Minimum Trace Widths
        2. 9.4.1.2 Layout Example
          1. 9.4.1.2.1 TPS25751AD Schematic Layout Example
          2. 9.4.1.2.2 TPS25751AD Layout Example - PCB Plots
            1. 9.4.1.2.2.1 TPS25751AD Component Placement
            2. 9.4.1.2.2.2 TPS25751AD PP5V
            3. 9.4.1.2.2.3 TPS25751AD PPHV
            4. 9.4.1.2.2.4 TPS25751AD VBUS
            5. 9.4.1.2.2.5 TPS25751AD I/O (I2C, ADCINs, GPIOs)
            6. 9.4.1.2.2.6 TPS25751AD DRAIN
            7. 9.4.1.2.2.7 TPS25751AD GND
      2. 9.4.2 TPS25751AS - Layout
        1. 9.4.2.1 Layout Guidelines
          1. 9.4.2.1.1 Recommended Via Size
          2. 9.4.2.1.2 Minimum Trace Widths
        2. 9.4.2.2 Layout Example
          1. 9.4.2.2.1 TPS25751AS Schematic Layout Example
          2. 9.4.2.2.2 TPS25751AS Layout Example - PCB Plots
            1. 9.4.2.2.2.1 TPS25751AS Component Placement
            2. 9.4.2.2.2.2 TPS25751AS PP5V
            3. 9.4.2.2.2.3 TPS25751AS PP_EXT
            4. 9.4.2.2.2.4 TPS25751AS VBUS
            5. 9.4.2.2.2.5 TPS25751AS I/O
            6. 9.4.2.2.2.6 TPS25751AS PPEXT Gate Driver
            7. 9.4.2.2.2.7 TPS25751AS GND
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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8.3.2 Power Management

The TPS25751A power management block receives power and generates voltages to provide power to the TPS25751A internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 can also be used as a low power output for external EEPROM memory. The power supply path is shown in Figure 8-11.

TPS25751A Power SuppliesFigure 8-11 Power Supplies

The TPS25751A is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. When powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3V circuitry and I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5V core digital circuitry. When VIN_3V3 power is unavailable and power is available on VBUS, the device is considered to be in the dead-battery start-up condition. In a dead-battery start-up condition, the TPS25751A opens the VIN_3V3 switch until the host clears the dead-battery flag through I2C. Therefore, the TPS25751A is powered from the VBUS input with the higher voltage during the dead-battery start-up condition and until the dead-battery flag is cleared. When powering from a VBUS input, the voltage on VBUS is stepped down through an LDO to LDO_3V3.