ZHCSMU0D July   2009  – December 2020 TPS23753A


  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Product Information
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Controller Section Only
    6. 7.6 Electrical Characteristics: PoE and Control
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Description
        1.  APD
        2.  BLNK
        3.  CLS
        4.  CS
        5.  CTL
        6.  DEN
        7.  FRS
        8.  GATE
        9.  RTN
        10. VB
        11. VC
        12. VDD
        13. VDD1
        14. VSS
    4. 8.4 Device Functional Modes
      1. 8.4.1  Threshold Voltages
      2. 8.4.2  PoE Start-Up Sequence
      3. 8.4.3  Detection
      4. 8.4.4  Hardware Classification
      5. 8.4.5  Maintain Power Signature (MPS)
      6. 8.4.6  TPS23753A Operation
        1. Start-Up and Converter Operation
        2. PD Self-Protection
        3. Converter Controller Features
      7. 8.4.7  Special Switching MOSFET Considerations
      8. 8.4.8  Thermal Considerations
      9. 8.4.9  FRS and Synchronization
      10. 8.4.10 Blanking – RBLNK
      11. 8.4.11 Current Slope Compensation
      12. 8.4.12 Adapter ORing
      13. 8.4.13 Protection
      14. 8.4.14 Frequency Dithering for Conducted Emissions Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Converter Controller Features

The TPS23753A DC-DC controller implements a typical current-mode control as shown in Figure 8-6. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft start, and gate driver. In addition, an internal current-compensation ramp generator, frequency synchronization logic, thermal shutdown, and start-up current source with control are provided.

The TPS23753A is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM and converter. There is an offset of VZDC (approximately 1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A VCTL below VZDC stops converter switching, while voltages above (VZDC + 2 × VCSMAX) does not increase the requested peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control range.

The internal start-up current source and control logic implement a bootstrap-type start-up. The start-up current source charges CVC from VDD1 when the converter is disabled (either by the PD control or the VC control), while operational power must come from a converter (bias winding) output. Loading on VC and VB must be minimal while CVC charges, otherwise the converter may never start. The optocoupler does not load VB when the converter is off. The converter shuts off when VC falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A restart initiates as described in Start-Up and Converter Operation if the converter turns off and there is sufficient VDD1 voltage. This type of operation is sometimes referred to as hiccup mode, which provides robust output short protection by providing time-average heating reduction of the output rectifier.

Take care in the design of the transformer and VC bias circuit to obtain hiccup overload protection. Leading-edge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected tracking with output voltage. RVC (Figure 9-1) is often required slow the peak charging. Good transformer bias-to-output-winding coupling results in reduced overshoot and better voltage tracking.

The start-up current source transitions to a resistance as (VDD1 – VC) falls below 7 V, but starts the converter from 12-V adapters within tST (VDD1 ≥ 10.2, tST approximately 85 ms). The converter starts from lower voltages, limited by the case when charge current equals the device bias current at voltage below the upper VC UVLO. The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual power loss of external resistors. The start-up current source does not charge above the maximum recommended VVC if the converter is disabled and there is sufficient VDD1 to charge higher.

The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 8-8 to increase slope compensation. This makes it easier to design the current limit to a fixed value.

The TPS23753A blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This avoids current-sense waveform distortion, which tends to get worse at light output loads. While the internally set blanking period is relatively precise, almost all converters require their own blanking period. The TPS23753A provides the BLNK pin to allow this programming. There may be some situations or designers that prefer an R-C approach. The TPS23753A provides a pulldown on CS during the GATE OFF-time to improve sensing when an R-C filter must be used. The CS input signal must be protected from nearby noisy signals like GATE drive and the MOSFET drain.

Converters require a soft start on the voltage error amplifier to prevent output overshoot on start-up. Figure 8-6 shows a common implementation of a secondary-side soft start that works with the typical TL431 error amplifier shown in Figure 9-1. This secondary-side error amplifier does not become active until there is sufficient voltage on the secondary. The TPS23753A provides a primary-side soft start, which persists long enough (approximately 800 μs) for secondary side voltage-loop soft start to take over; however, the actual start-up is typically shorter than this. The primary-side current-loop soft-start controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. The lower of the CTL and soft-start ramps controls the PWM comparator. Figure 8-4 shows an exaggerated handoff between the primary and secondary-side soft start that is most easily seen in the IPI waveform. The output voltage rises in a smooth monotonic fashion with no overshoot. The soft-start handoff in this example could have been optimized by decreasing the secondary-side soft-start period.

GUID-3B366CDC-B63B-4052-A40B-E705BECBE4E8-low.gifFigure 8-6 Example of Soft-Start Circuit Added to Error Amplifier

The DC-DC controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver, bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, resets the soft-start generator, and forces the VC control into an undervoltage state.