ZHCSCB9E April 2014 – July 2022 TPS22965-Q1
Due to the integrated body diode in the NMOS switch, TI highly recommends a CIN greater than CL. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This event can result in current flow through the body diode from VOUT to VIN. TI recommends a CIN to CL ratio of 10 to 1 for minimizing VIN dip caused by inrush currents during startup; however, a 10 to 1 ratio for capacitance is not required for proper functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) can cause slightly more VIN dip upon turn-on due to inrush currents. This event can be mitigated by increasing the capacitance on the CT pin for a longer rise time (see the Adjustable Rise Time section).