ZHCSM60B september   2021  – august 2023 TMUX8108 , TMUX8109

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings: TMUX810x Devices
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: TMUX810x Devices
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics (Global): TMUX810x Devices
    6. 7.6  Electrical Characteristics (±15-V Dual Supply)
    7. 7.7  Electrical Characteristics (±36-V Dual Supply)
    8. 7.8  Electrical Characteristics (±50-V Dual Supply)
    9. 7.9  Electrical Characteristics (72-V Single Supply)
    10. 7.10 Electrical Characteristics (100-V Single Supply)
    11. 7.11 Switching Characteristics: TMUX810x Devices
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Break-Before-Make Delay
    5. 8.5  Enable Turn-on and Turn-off Time
    6. 8.6  Transition Time
    7. 8.7  Charge Injection
    8. 8.8  Off Isolation
    9. 8.9  Crosstalk
    10. 8.10 Bandwidth
    11. 8.11 THD + Noise
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Flat On – Resistance
      3. 9.3.3 Protection Features
        1. 9.3.3.1 Fail-Safe Logic
        2. 9.3.3.2 ESD Protection
        3. 9.3.3.3 Latch-Up Immunity
      4. 9.3.4 1.8 V Logic Compatible Inputs
      5. 9.3.5 Integrated Pull-Down Resistor on Logic Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Truth Tables
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PW|16
  • RUM|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

GUID-45892D94-3FAD-4DC0-A66A-CD70364AA557-low.gifFigure 6-1 PW Package, 16-Pin TSSOP (Top View)
GUID-37F66FC0-44FE-49FF-A567-7FAE1F91525D-low.gifFigure 6-2 RUM Package 16-Pin WQFN (Top View)
Table 6-1 Pin Functions: TMUX8108
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
A0 1 15 I Logic control input address 0 (A0).
EN 2 16 I Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
S1 4 2 I/O Source pin 1. Can be an input or output.
S2 5 3 I/O Source pin 2. Can be an input or output.
S3 6 4 I/O Source pin 3. Can be an input or output.
S4 7 5 I/O Source pin 4. Can be an input or output.
D 8 6 I/O Drain pin. Can be an input or output.
S8 9 7 I/O Source pin 8. Can be an input or output.
S7 10 8 I/O Source pin 7. Can be an input or output.
S6 11 9 I/O Source pin 6. Can be an input or output.
S5 12 10 I/O Source pin 5. Can be an input or output.
VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND 14 12 P Ground (0 V) reference
A2 15 13 I Logic control input address 2 (A2).
A1 16 14 I Logic control input address 1 (A1).
Thermal Pad — The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for the best performance.
(1) I = input, O = output, I/O = input and output, P = power
GUID-9327CA30-859F-4F87-BB1A-DDD41F916120-low.gifFigure 6-3 PW Package, 16-Pin TSSOP (Top View)
GUID-5F8702B1-0ED7-4449-BB1C-00260CC4B7F2-low.gifFigure 6-4 RUM Package, 16-Pin WQFN (Top View)
Table 6-2 Pin Functions: TMUX8109
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
A0 1 15 I Logic control input address 0 (A0).
EN 2 16 I Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
S1A 4 2 I/O Source pin 1A. Can be an input or output.
S2A 5 3 I/O Source pin 2A. Can be an input or output.
S3A 6 4 I/O Source pin 3A. Can be an input or output.
S4A 7 5 I/O Source pin 4A. Can be an input or output.
DA 8 6 I/O Drain terminal A. Can be an input or output.
DB 9 7 I/O Drain terminal B. Can be an input or output
S4B 10 8 I/O Source pin 4B. Can be an input or output.
S3B 11 9 I/O Source pin 3B. Can be an input or output.
S2B 12 10 I/O Source pin 2B. Can be an input or output.
S1B 13 11 I/O Source pin 1B. Can be an input or output.
VDD 14 12 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND 15 13 P Ground (0 V) reference
A1 16 14 I Logic control input address 1 (A1).
Thermal Pad — The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for the best performance.
(1) I = input, O = output, I/O = input and output, P = power