ZHCSJS3C May   2019  – November 2020 TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pins With Internal Pullup and Pulldown
    5. 6.5 Pin Multiplexing
      1. 6.5.1 GPIO Muxed Pins Table
      2. 6.5.2 Input X-BAR
      3. 6.5.3 Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
      4. 6.5.4 USB Pin Muxing
      5. 6.5.5 High-Speed SPI Pin Muxing
      6. 6.5.6 High-Speed SSI Pin Muxing
    6. 6.6 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for ZWT Package
    8. 7.8  Thermal Resistance Characteristics for PTP Package
    9. 7.9  Thermal Design Considerations
    10. 7.10 System
      1. 7.10.1 Power Sequencing
      2. 7.10.2 Reset Timing
        1. 7.10.2.1 Reset Sources
        2. 7.10.2.2 Reset Electrical Data and Timing
          1. 7.10.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.10.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.10.2.2.3 Reset Timing Diagrams
      3. 7.10.3 Clock Specifications
        1. 7.10.3.1 Clock Sources
        2. 7.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.10.3.2.1.1 Input Clock Frequency
            2. 7.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.10.3.2.1.3 X1 Timing Requirements
            4. 7.10.3.2.1.4 AUXCLKIN Timing Requirements
            5. 7.10.3.2.1.5 APLL Characteristics
          2. 7.10.3.2.2 Internal Clock Frequencies
            1. 7.10.3.2.2.1 Internal Clock Frequencies
          3. 7.10.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.10.3.2.3.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 7.10.3.3 Input Clocks
        4. 7.10.3.4 Crystal Oscillator
          1. 7.10.3.4.1 Crystal Oscillator Parameters
          2. 7.10.3.4.2 Crystal Equivalent Series Resistance (ESR) Requirements Table
          3. 7.10.3.4.3 Crystal Oscillator Electrical Characteristics
        5. 7.10.3.5 Internal Oscillators
          1. 7.10.3.5.1 INTOSC Characteristics
      4. 7.10.4 Flash Parameters
      5. 7.10.5 Emulation/JTAG
        1. 7.10.5.1 JTAG Electrical Data and Timing
          1. 7.10.5.1.1 JTAG Timing Requirements
          2. 7.10.5.1.2 JTAG Switching Characteristics
          3. 7.10.5.1.3 JTAG Timing
      6. 7.10.6 GPIO Electrical Data and Timing
        1. 7.10.6.1 GPIO - Output Timing
          1. 7.10.6.1.1 General-Purpose Output Switching Characteristics
          2. 7.10.6.1.2 General-Purpose Output Timing
        2. 7.10.6.2 GPIO - Input Timing
          1. 7.10.6.2.1 General-Purpose Input Timing Requirements
          2. 7.10.6.2.2 Sampling Mode
        3. 7.10.6.3 Sampling Window Width for Input Signals
      7. 7.10.7 Interrupts
        1. 7.10.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.10.7.1.1 External Interrupt Timing Requirements
          2. 7.10.7.1.2 External Interrupt Switching Characteristics
          3. 7.10.7.1.3 External Interrupt Timing
      8. 7.10.8 Low-Power Modes
        1. 7.10.8.1 Clock-Gating Low-Power Modes
        2. 7.10.8.2 Low-Power Mode Wakeup Timing
          1. 7.10.8.2.1 IDLE Mode Timing Requirements
          2. 7.10.8.2.2 IDLE Mode Switching Characteristics
          3. 7.10.8.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.10.8.2.4 STANDBY Mode Timing Requirements
          5. 7.10.8.2.5 STANDBY Mode Switching Characteristics
          6. 7.10.8.2.6 STANDBY Entry and Exit Timing Diagram
      9. 7.10.9 External Memory Interface (EMIF)
        1. 7.10.9.1 Asynchronous Memory Support
        2. 7.10.9.2 Synchronous DRAM Support
        3. 7.10.9.3 EMIF Electrical Data and Timing
          1. 7.10.9.3.1 Asynchronous RAM
            1. 7.10.9.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 7.10.9.3.1.2 EMIF Asynchronous Memory Switching Characteristics
            3. 7.10.9.3.1.3 EMIF Asynchronous Memory Timing Diagrams
          2. 7.10.9.3.2 Synchronous RAM
            1. 7.10.9.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 7.10.9.3.2.2 EMIF Synchronous Memory Switching Characteristics
            3. 7.10.9.3.2.3 EMIF Synchronous Memory Timing Diagrams
    11. 7.11 C28x Analog Peripherals
      1. 7.11.1 Analog Subsystem
      2. 7.11.2 Analog-to-Digital Converter (ADC)
        1. 7.11.2.1 Result Register Mapping
        2. 7.11.2.2 ADC Configurability
          1. 7.11.2.2.1 Signal Mode
        3. 7.11.2.3 ADC Electrical Data and Timing
          1. 7.11.2.3.1 ADC Operating Conditions (16-bit Differential)
            1. 7.11.2.3.1.1 ADC Operating Conditions (16-bit Differential) Notes
          2. 7.11.2.3.2 ADC Characteristics (16-bit Differential)
          3. 7.11.2.3.3 ADC Operating Conditions (16-bit Single-Ended)
            1. 7.11.2.3.3.1 ADC Operating Conditions (16-bit Single-Ended) Notes
          4. 7.11.2.3.4 ADC Characteristics (16-bit Single-Ended)
          5. 7.11.2.3.5 ADC Operating Conditions (12-bit Single-Ended)
            1. 7.11.2.3.5.1 ADC Operating Conditions (12-bit Single-Ended) Notes
          6. 7.11.2.3.6 ADC Characteristics (12-bit Single-Ended)
          7. 7.11.2.3.7 ADCEXTSOC Timing Requirements
          8. 7.11.2.3.8 ADC Input Models
            1. 7.11.2.3.8.1 Single-Ended Input Model Parameters (12-bit Resolution)
            2. 7.11.2.3.8.2 Single-Ended Input Model Parameters (16-bit Resolution)
            3. 7.11.2.3.8.3 Single-Ended Input Model
            4. 7.11.2.3.8.4 Differential Input Model Parameters (16-bit Resolution)
            5. 7.11.2.3.8.5 Differential Input Model
          9. 7.11.2.3.9 ADC Timing Diagrams
            1. 7.11.2.3.9.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 7.11.2.3.9.2 ADC Timings in 16-Bit Mode
        4. 7.11.2.4 Temperature Sensor Electrical Data and Timing
          1. 7.11.2.4.1 Temperature Sensor Characteristics
      3. 7.11.3 Comparator Subsystem (CMPSS)
        1. 7.11.3.1 CMPSS Electrical Data and Timing
          1. 7.11.3.1.1 Comparator Electrical Characteristics
          2. 7.11.3.1.2 CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.11.3.1.3 CMPSS DAC Static Electrical Characteristics
          4. 7.11.3.1.4 CMPSS Illustrative Graphs
      4. 7.11.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.11.4.1 Buffered DAC Electrical Data and Timing
          1. 7.11.4.1.1 Buffered DAC Operating Conditions
          2. 7.11.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.11.4.1.3 Buffered DAC Notes and Illustrative Graphs
    12. 7.12 C28x Control Peripherals
      1. 7.12.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.12.1.1 eCAP Synchronization
        2. 7.12.1.2 eCAP Electrical Data and Timing
          1. 7.12.1.2.1 eCAP Timing Requirements
          2. 7.12.1.2.2 eCAP Switching Charcteristics
        3. 7.12.1.3 HRCAP Electrical Data and Timing
          1. 7.12.1.3.1 HRCAP Switching Characteristics
          2. 7.12.1.3.2 HRCAP Graphs
      2. 7.12.2 Enhanced Pulse Width Modulator (ePWM)
        1. 7.12.2.1 Control Peripherals Synchronization
        2. 7.12.2.2 ePWM Electrical Data and Timing
          1. 7.12.2.2.1 ePWM Timing Requirements
          2. 7.12.2.2.2 ePWM Switching Characteristics
          3. 7.12.2.2.3 Trip-Zone Input Timing
            1. 7.12.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.12.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.12.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 7.12.3 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.12.3.1 HRPWM Electrical Data and Timing
          1. 7.12.3.1.1 High-Resolution PWM Characteristics
      4. 7.12.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.12.4.1 eQEP Electrical Data and Timing
          1. 7.12.4.1.1 eQEP Timing Requirements
          2. 7.12.4.1.2 eQEP Switching Characteristics
      5. 7.12.5 Sigma-Delta Filter Module (SDFM)
        1. 7.12.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 7.12.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.12.5.1.2 SDFM Timing Diagram
    13. 7.13 C28x Communications Peripherals
      1. 7.13.1 Controller Area Network (CAN)
      2. 7.13.2 Fast Serial Interface (FSI)
        1. 7.13.2.1 FSI Transmitter
          1. 7.13.2.1.1 FSITX Electrical Data and Timing
            1. 7.13.2.1.1.1 FSITX Switching Characteristics
            2. 7.13.2.1.1.2 FSITX Timings
        2. 7.13.2.2 FSI Receiver
          1. 7.13.2.2.1 FSIRX Electrical Data and Timing
            1. 7.13.2.2.1.1 FSIRX Timing Requirements
            2. 7.13.2.2.1.2 FSIRX Switching Characteristics
            3. 7.13.2.2.1.3 FSIRX Timing Diagram
        3. 7.13.2.3 SPI Signaling Mode
          1. 7.13.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.13.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.13.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 7.13.3 Inter-Integrated Circuit (I2C)
        1. 7.13.3.1 I2C Electrical Data and Timing
          1. 7.13.3.1.1 I2C Timing Requirements
          2. 7.13.3.1.2 I2C Switching Characteristics
          3. 7.13.3.1.3 I2C Timing Diagram
      4. 7.13.4 Multichannel Buffered Serial Port (McBSP)
        1. 7.13.4.1 McBSP Electrical Data and Timing
          1. 7.13.4.1.1 McBSP Transmit and Receive Timing
            1. 7.13.4.1.1.1 McBSP Timing Requirements
            2. 7.13.4.1.1.2 McBSP Switching Characteristics
            3. 7.13.4.1.1.3 McBSP Receive and Transmit Timing Diagrams
          2. 7.13.4.1.2 McBSP as SPI Master or Slave Timing
            1. 7.13.4.1.2.1 McBSP as SPI Master Timing Requirements
            2. 7.13.4.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 7.13.4.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 7.13.4.1.2.4 McBSP as SPI Slave Switching Characteristics
            5. 7.13.4.1.2.5 McBSP as SPI Master or Slave Timing Diagrams
      5. 7.13.5 Power Management Bus (PMBus)
        1. 7.13.5.1 PMBus Electrical Data and Timing
          1. 7.13.5.1.1 PMBus Electrical Characteristics
          2. 7.13.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.13.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 7.13.6 Serial Communications Interface (SCI)
      7. 7.13.7 Serial Peripheral Interface (SPI)
        1. 7.13.7.1 SPI Electrical Data and Timing
          1. 7.13.7.1.1 SPI Master Mode Timings
            1. 7.13.7.1.1.1 SPI Master Mode Timing Requirements
            2. 7.13.7.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 7.13.7.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            4. 7.13.7.1.1.4 SPI Master Mode External Timing
          2. 7.13.7.1.2 SPI Slave Mode Timings
            1. 7.13.7.1.2.1 SPI Slave Mode Timing Requirements
            2. 7.13.7.1.2.2 SPI Slave Mode Switching Characteristics
            3. 7.13.7.1.2.3 SPI Slave Mode External Timing
      8. 7.13.8 EtherCAT Slave Controller (ESC)
        1. 7.13.8.1 ESC Features
        2. 7.13.8.2 ESC Subsystem Integrated Features
        3. 7.13.8.3 EtherCAT IP Block Diagram
        4. 7.13.8.4 EtherCAT Electrical Data and Timing
          1. 7.13.8.4.1 EtherCAT Timing Requirements
          2. 7.13.8.4.2 EtherCAT Switching Characteristics
          3. 7.13.8.4.3 EtherCAT Timing Diagrams
      9. 7.13.9 Universal Serial Bus (USB) Controller
        1. 7.13.9.1 USB Electrical Data and Timing
          1. 7.13.9.1.1 USB Input Ports DP and DM Timing Requirements
          2. 7.13.9.1.2 USB Output Ports DP and DM Switching Characteristics
    14. 7.14 Connectivity Manager (CM) Peripherals
      1. 7.14.1 Modular Controller Area Network (MCAN) [CAN FD]
      2. 7.14.2 Ethernet Media Access Controller (EMAC)
        1. 7.14.2.1 MAC Features
          1. 7.14.2.1.1 MAC Tx and Rx Features
          2. 7.14.2.1.2 MAC Tx Features
          3. 7.14.2.1.3 MAC Rx Features
        2. 7.14.2.2 Ethernet Electrical Data and Timing
          1. 7.14.2.2.1 Ethernet Timing Requirements
          2. 7.14.2.2.2 Ethernet Switching Characteristics
          3. 7.14.2.2.3 Ethernet Timing Diagrams
        3. 7.14.2.3 Ethernet REVMII Electrical Data and Timing
          1. 7.14.2.3.1 Ethernet REVMII Timing Requirements
          2. 7.14.2.3.2 Ethernet REVMII Switching Characteristics
      3. 7.14.3 Inter-Integrated Circuit (CM-I2C)
        1. 7.14.3.1 CM-I2C Electrical Data and Timing
          1. 7.14.3.1.1 CM-I2C Timing Requirements
          2. 7.14.3.1.2 CM-I2C Switching Characteristics
          3. 7.14.3.1.3 CM-I2C Timing Diagram
      4. 7.14.4 Synchronous Serial Interface (SSI)
        1. 7.14.4.1 SSI Electrical Data and Timing
          1. 7.14.4.1.1 SSI Timing Requirements
          2. 7.14.4.1.2 SSI Characteristics
          3. 7.14.4.1.3 SSI Timing Diagrams
      5. 7.14.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
      6. 7.14.6 Trace Port Interface Unit (TPIU)
        1. 7.14.6.1 TPIU Electrical Data and Timing
          1. 7.14.6.1.1 Trace Port Switching Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 C28x Flash Memory Map
      3. 8.3.3 EMIF Chip Select Memory Map
      4. 8.3.4 CM Memory Map
      5. 8.3.5 CM Flash Memory Map
      6. 8.3.6 Memory Types
        1. 8.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 8.3.6.2 Local Shared RAM (LSx RAM)
        3. 8.3.6.3 Global Shared RAM (GSx RAM)
        4. 8.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 8.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 8.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
        7. 8.3.6.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
        8. 8.3.6.8 Dedicated RAM (C0/C1 RAM)
        9. 8.3.6.9 Shared RAM (E0 and Sx RAM)
    4. 8.4 Identification
    5. 8.5 Bus Architecture – Peripheral Connectivity
    6. 8.6 Boot ROM and Peripheral Booting
      1. 8.6.1 Device Boot
      2. 8.6.2 Device Boot Modes
      3. 8.6.3 Device Boot Configurations
      4. 8.6.4 GPIO Assignments for CPU1
    7. 8.7 Dual Code Security Module (DCSM)
    8. 8.8 C28x (CPU1/CPU2) Subsystem
      1. 8.8.1  C28x Processor
        1. 8.8.1.1 Floating-Point Unit
        2. 8.8.1.2 Trigonometric Math Unit
        3. 8.8.1.3 Fast Integer Division Unit
        4. 8.8.1.4 VCRC Unit
      2. 8.8.2  Embedded Real-Time Analysis and Diagnostic (ERAD)
      3. 8.8.3  Background CRC-32 (BGCRC)
      4. 8.8.4  Control Law Accelerator (CLA)
      5. 8.8.5  Direct Memory Access (DMA)
      6. 8.8.6  Interprocessor Communication (IPC) Module
      7. 8.8.7  C28x Timers
      8. 8.8.8  Dual-Clock Comparator (DCC)
        1. 8.8.8.1 Features
        2. 8.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
      9. 8.8.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 8.8.10 Watchdog
      11. 8.8.11 Configurable Logic Block (CLB)
    9. 8.9 Connectivity Manager (CM) Subsystem
      1. 8.9.1  Arm Cortex-M4 Processor
      2. 8.9.2  Nested Vectored Interrupt Controller (NVIC)
      3. 8.9.3  Advance Encryption Standard (AES) Accelerator
      4. 8.9.4  Generic Cyclic Redundancy Check (GCRC) Module
      5. 8.9.5  CM Nonmaskable Interrupt (CMNMI) Module
      6. 8.9.6  Memory Protection Unit (MPU)
      7. 8.9.7  Micro Direct Memory Access (µDMA)
      8. 8.9.8  Watchdog
      9. 8.9.9  CM Clocking
        1. 8.9.9.1 CM Clock Sources
      10. 8.9.10 CM Timers
  9. Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Markings
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZWT|337
  • PTP|176
散热焊盘机械数据 (封装 | 引脚)
订购信息

特性

  • 双核 C28x 架构
    • 两个 TMS320C28x 32 位 CPU
      • 200MHz
      • IEEE 754 双精度(64 位)浮点单元 (FPU)
      • 三角法数学单元 (TMU)
      • CRC 引擎和指令 (VCRC)
      • 快速整数除法 (FINTDIV)
    • 每个 CPU 各有 512KB (256KW) 闪存
      (受 ECC 保护)
    • 每个 CPU 各有 44KB (22KW) 的本机 RAM
    • 两个 CPU 共享 128KB (64KW) 的全局 RAM(受奇偶校验保护)
  • 两个控制律加速器 (CLA)
    • 200MHz
    • IEEE 754 单精度浮点单元
    • 独立于 C28x CPU 之外执行代码
  • 系统外设
    • 两个支持 ASRAM 和 SDRAM 的外部存储器接口 (EMIF)
    • 两个 6 通道直接存储器存取 (DMA) 控制器
    • 多达 169 个支持输入滤波的通用输入/输出 (GPIO) 引脚
    • 扩展外设中断控制器 (ePIE)
    • 支持低功耗模式 (LPM)
    • 支持第三方开发的双区安全
    • 唯一标识 (UID) 号
    • 嵌入式实时分析和诊断 (ERAD)
    • 背景 CRC (BGCRC)
  • 连接管理器 (CM)
    • Arm® Cortex®-M4 处理器
    • 125MHz
    • 512KB 的闪存(受 ECC 保护)
    • 96KB 的 RAM(受 ECC 保护或奇偶校验保护)
    • 高级加密标准 (AES) 加速器
    • 通用 CRC (GCRC)
    • 32 通道微型直接存储器存取 (µDMA) 控制器
    • 通用异步接收器/发送器 (CM-UART)
    • 内部集成电路 (CM-I2C)
    • 同步串行接口 (SSI)
    • 10/100 以太网 1588 MII/RMII
    • MCAN (CAN-FD)
  • C28x 通信外设
    • 带两个发送器和八个接收器的快速串行接口 (FSI)
    • 四个高速(最高 50MHz)SPI 端口(引脚可引导)
    • 四个串行通信接口 (SCI/UART)(引脚可引导)
    • 两个 I2C 接口(引脚可引导)
    • 电源管理总线 (PMBus) 接口
    • 两个多通道缓冲串行端口 (McBSP)
  • CM-C28x 共享通信外设
    • EtherCAT® 从站控制器 (ESC)
    • USB 2.0 (MAC + PHY)
    • 两个控制器局域网 (CAN) 模块(引脚可引导)
  • 模拟子系统
    • 四个模数转换器 (ADC)
      • 16 位模式
        • 每个转换器的吞吐量为 1.1MSPS
        • 12 个差动输入或 24 个单端输入
      • 12 位模式
        • 每个转换器的吞吐量为 3.5MSPS
        • 24 个单端输入
      • 每个 ADC 上有一个采样保持 (S/H) 电路
      • 转换的硬件后处理
    • 八个具有 12 位数模转换器 (DAC) 参考的窗口比较器
    • 三个 12 位缓冲 DAC 输出
  • 控制外设
    • 32 个脉宽调制器 (PWM) 通道
      • 8 个 PWM 模块的 A 和 B 通道(16 个通道)均可实现高分辨率
      • 死区支持(对于标准和高分辨率均支持)
    • 七个增强型捕捉 (eCAP) 模块
      • 在七个 eCAP 模块中,有两个提供高分辨率捕捉 (HRCAP)
    • 三个增强型正交编码器脉冲 (eQEP) 模块
    • 八个 Σ-Δ 滤波器模块 (SDFM) 输入通道,每个通道 2 个独立滤波器
  • 可配置逻辑块 (CLB)
    • 增强现有外设功能
    • 支持位置管理器解决方案
  • 时钟和系统控制
    • 两个内部零引脚 10MHz 振荡器
    • 片上晶体振荡器
    • 窗口化看门狗计时器模块
    • 丢失时钟检测电路
    • 双路时钟比较器 (DCC)
  • 1.2V 内核、3.3V I/O 设计
  • 封装选项:
    • 无铅,绿色环保封装
    • 337 球全新细间距球栅阵列 (nFBGA) [后缀 ZWT]
    • 176 引脚 PowerPAD™ 散热增强型薄型四方扁平封装 (HLQFP) [PTP 后缀]
  • 温度选项:
    • S:–40°C 至 125°C 结温
    • Q:–40°C 至 125°C 的环境温度范围
      (通过针对汽车应用的 AEC Q100 认证)