ZHCSA18F March   2009  – February 2021 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28343-Q1 , TMS320C28344 , TMS320C28345 , TMS320C28346 , TMS320C28346-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1) (1)
    2. 7.2 ESD Ratings – Automotive
    3. 7.3 ESD Ratings – Commercial
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Consumption Summary
      1. 7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. 7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
    6. 7.6 Electrical Characteristics
    7. 7.7 Thermal Resistance Characteristics
      1. 7.7.1 ZHH Package
      2. 7.7.2 ZFE Package
    8. 7.8 Thermal Design Considerations
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset ( XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. 7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. 7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.3.4 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements (1)
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements (1)
          2. 7.9.4.3.2 External Interrupt Switching Characteristics (1)
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (1) (1) (1) (1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (1) (1) (1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements (1) (1)
            2. 7.9.4.6.1.2 McBSP Switching Characteristics (1) (1)
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
      5. 7.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 1-1
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (1) (1) (1)
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  M0, M1 SARAMs
      7. 8.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 8.1.8  Boot ROM
      9. 8.1.9  Security
      10. 8.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 8.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 8.1.12 Oscillator and PLL
      13. 8.1.13 Watchdog
      14. 8.1.14 Peripheral Clocking
      15. 8.1.15 Low-Power Modes
      16. 8.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 8.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 8.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 8.1.19 Control Peripherals
      20. 8.1.20 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  External ADC Interface
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Design or Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

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8.2.3 Enhanced PWM Modules

The devices contain up to nine enhanced PWM (ePWM) modules (ePWM1 to ePWM9). Figure 8-4 shows a block diagram of multiple ePWM modules. Figure 8-5 shows the signal interconnections with the ePWM.

Table 8-3 and Table 8-4 show the complete ePWM register set per module .

GUID-4CA27C02-5537-441E-B823-68759A9F1C50-low.gifFigure 8-4 Generation of SOC Pulses to the External ADC Module
Table 8-3 ePWM1–ePWM4 Control and Status Registers
NAMEePWM1ePWM2ePWM3ePWM4SIZE (x16) / #SHADOWDESCRIPTION
TBCTL0x68000x68400x68800x68C01 / 0Time Base Control Register
TBSTS0x68010x68410x68810x68C11 / 0Time Base Status Register
TBPHSHR0x68020x68420x68820x68C21 / 0Time Base Phase HRPWM Register
TBPHS0x68030x68430x68830x68C31 / 0Time Base Phase Register
TBCTR0x68040x68440x68840x68C41 / 0Time Base Counter Register
TBPRD0x68050x68450x68850x68C51 / 1Time Base Period Register Set
CMPCTL0x68070x68470x68870x68C71 / 0Counter Compare Control Register
CMPAHR0x68080x68480x68880x68C81 / 1Time Base Compare A HRPWM Register
CMPA0x68090x68490x68890x68C91 / 1Counter Compare A Register Set
CMPB0x680A0x684A0x688A0x68CA1 / 1Counter Compare B Register Set
AQCTLA0x680B0x684B0x688B0x68CB1 / 0Action Qualifier Control Register For Output A
AQCTLB0x680C0x684C0x688C0x68CC1 / 0Action Qualifier Control Register For Output B
AQSFRC0x680D0x684D0x688D0x68CD1 / 0Action Qualifier Software Force Register
AQCSFRC0x680E0x684E0x688E0x68CE1 / 1Action Qualifier Continuous S/W Force Register Set
DBCTL0x680F0x684F0x688F0x68CF1 / 1Dead-Band Generator Control Register
DBRED0x68100x68500x68900x68D01 / 0Dead-Band Generator Rising Edge Delay Count Register
DBFED0x68110x68510x68910x68D11 / 0Dead-Band Generator Falling Edge Delay Count Register
TZSEL0x68120x68520x68920x68D21 / 0Trip Zone Select Register(1)
TZCTL0x68140x68540x68940x68D41 / 0Trip Zone Control Register(1)
TZEINT0x68150x68550x68950x68D51 / 0Trip Zone Enable Interrupt Register(1)
TZFLG0x68160x68560x68960x68D61 / 0Trip Zone Flag Register
TZCLR0x68170x68570x68970x68D71 / 0Trip Zone Clear Register(1)
TZFRC0x68180x68580x68980x68D81 / 0Trip Zone Force Register(1)
ETSEL0x68190x68590x68990x68D91 / 0Event Trigger Selection Register
ETPS0x681A0x685A0x689A0x68DA1 / 0Event Trigger Prescale Register
ETFLG0x681B0x685B0x689B0x68DB1 / 0Event Trigger Flag Register
ETCLR0x681C0x685C0x689C0x68DC1 / 0Event Trigger Clear Register
ETFRC0x681D0x685D0x689D0x68DD1 / 0Event Trigger Force Register
PCCTL0x681E0x685E0x689E0x68DE1 / 0PWM Chopper Control Register
HRCNFG0x68200x68600x68A00x68E01 / 0HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
Table 8-4 ePWM5–ePWM9 Control and Status Registers
NAMEePWM5ePWM6ePWM7ePWM8ePWM9SIZE (x16) / #SHADOWDESCRIPTION
TBCTL0x69000x69400x69800x69C00x66001 / 0Time Base Control Register
TBSTS0x69010x69410x69810x69C10x66011 / 0Time Base Status Register
TBPHSHR0x69020x69420x69820x69C20x66021 / 0Time Base Phase HRPWM Register
TBPHS0x69030x69430x69830x69C30x66031 / 0Time Base Phase Register
TBCTR0x69040x69440x69840x69C40x66041 / 0Time Base Counter Register
TBPRD0x69050x69450x69850x69C50x66051 / 1Time Base Period Register Set
CMPCTL0x69070x69470x69870x69C70x66071 / 0Counter Compare Control Register
CMPAHR0x69080x69480x69880x69C80x66081 / 1Time Base Compare A HRPWM Register
CMPA0x69090x69490x69890x69C90x66091 / 1Counter Compare A Register Set
CMPB0x690A0x694A0x698A0x69CA0x660A1 / 1Counter Compare B Register Set
AQCTLA0x690B0x694B0x698B0x69CB0x660B1 / 0Action Qualifier Control Register For Output A
AQCTLB0x690C0x694C0x698C0x69CC0x660C1 / 0Action Qualifier Control Register For Output B
AQSFRC0x690D0x694D0x698D0x69CD0x660D1 / 0Action Qualifier Software Force Register
AQCSFRC0x690E0x694E0x698E0x69CE0x660E1 / 1Action Qualifier Continuous S/W Force Register Set
DBCTL0x690F0x694F0x698F0x69CF0x660F1 / 1Dead-Band Generator Control Register
DBRED0x69100x69500x69900x69D00x66101 / 0Dead-Band Generator Rising Edge Delay Count Register
DBFED0x69110x69510x69910x69D10x66111 / 0Dead-Band Generator Falling Edge Delay Count Register
TZSEL0x69120x69520x69920x69D20x66121 / 0Trip Zone Select Register(1)
TZCTL0x69140x69540x69940x69D40x66141 / 0Trip Zone Control Register(1)
TZEINT0x69150x69550x69950x69D50x66151 / 0Trip Zone Enable Interrupt Register(1)
TZFLG0x69160x69560x69960x69D60x66161 / 0Trip Zone Flag Register
TZCLR0x69170x69570x69970x69D70x66171 / 0Trip Zone Clear Register(1)
TZFRC0x69180x69580x69980x69D80x66181 / 0Trip Zone Force Register(1)
ETSEL0x69190x69590x69990x69D90x66191 / 0Event Trigger Selection Register
ETPS0x691A0x695A0x699A0x69DA0x661A1 / 0Event Trigger Prescale Register
ETFLG0x691B0x695B0x699B0x69DB0x661B1 / 0Event Trigger Flag Register
ETCLR0x691C0x695C0x699C0x69DC0x661C1 / 0Event Trigger Clear Register
ETFRC0x691D0x695D0x699D0x69DD0x661D1 / 0Event Trigger Force Register
PCCTL0x691E0x695E0x699E0x69DE0x661E1 / 0PWM Chopper Control Register
HRCNFG0x69200x69600x69A00x69E00x66201 / 0HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
GUID-E9D464F6-9D31-4770-A9D4-8CE7273C07C6-low.gifFigure 8-5 ePWM Submodules Showing Critical Internal Signal Interconnections