ZHCSHX6C August   2017  – February 2023 THS3491

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Bare Die Information
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: VS = ±15 V
    6. 8.6 Electrical Characteristics: VS = ±7.5 V
    7. 8.7 Typical Characteristics: ±15 V
    8. 8.8 Typical Characteristics: ±7.5 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Down (PD) Pin
      2. 9.3.2 Power-Down Reference (REF) Pin
      3. 9.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 9.4 Device Functional Modes
      1. 9.4.1 Wideband Noninverting Operation
      2. 9.4.2 Wideband, Inverting Operation
      3. 9.4.3 Single-Supply Operation
      4. 9.4.4 Maximum Recommended Output Voltage
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driving Capacitive Loads
      2. 10.1.2 Video Distribution
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
          1. 10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
          2. 10.4.1.1.2 Power Dissipation and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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10.1.1 Driving Capacitive Loads

Applications such as power JFET and MOSFET (power FET) drivers are highly capacitive and cause stability problems for high-speed amplifiers.

Figure 10-1 and Figure 10-2 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier feedback path. The output impedance of the amplifier in conjunction with CLOAD introduces a pole in the open-loop transimpedance gain response and if the pole is at a frequency lower than the non-dominant pole of the amplifier, then this results in a reduced loop gain and a reduced phase margin. The isolation resistor introduces a zero in the response, which counteracts the effect of the pole. The location of the zero is dependent on the values of RISO and CLOAD. Figure 8-5 shows examples of the recommended RISO values to achieve flat frequency response while driving certain capacitive loads. See Effect of Parasitic Capacitance in Op Amp Circuits for a detailed analysis of selecting isolation resistor values while driving capacitive loads.

GUID-76C31FB7-214D-4846-82C3-9767DEA10700-low.gifFigure 10-1 Driving a Large Capacitive Load Using an Output Series Isolation Resistor

Placing a small series resistor (RISO) between the output of the amplifier and the capacitive load as Figure 10-1 shows is a simple way to isolate the load capacitance.

Figure 10-2 shows two amplifiers in parallel to double the output drive current in order to drive larger capacitive loads. This technique is used when more output current is required to charge and discharge the load faster, such as driving large FET transistors.

GUID-847C704F-B710-4949-A096-DAE8DDC4E59D-low.gifFigure 10-2 Driving a Large Capacitive Load Using Two Parallel Amplifier Channels

Figure 10-3 shows a push-pull FET driver circuit commonly used in ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier.

GUID-A820E3E6-84E5-4BF8-898D-B3B70E593972-low.gifFigure 10-3 Power FET Drive Circuit