ZHCSCU3C January   2014  – September 2019 TCA5013

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics—Power Supply and ESD
    6. 6.6  Electrical Characteristics—Card VCC
    7. 6.7  Electrical Characteristics—Card RST
    8. 6.8  Electrical Characteristics—Card CLK
    9. 6.9  Electrical Characteristics—Card Interface IO, C4 and C8
    10. 6.10 Electrical Characteristics—PRES
    11. 6.11 Electrical Characteristics—IOMC1 and IOMC2
    12. 6.12 Electrical Characteristics—CLKIN1 and CLKIN2
    13. 6.13 Electrical Characteristics—A0 and SHDN
    14. 6.14 Electrical Characteristics—INT
    15. 6.15 Electrical Characteristics—GPIO
    16. 6.16 Electrical Characteristics—SDA and SCL
    17. 6.17 Electrical Characteristics—Fault Condition Detection
    18. 6.18 I2C Interface Timing Requirements
    19. 6.19 I2C Interface Timing Characteristics
    20. 6.20 Synchronous Type 1 Card Activation Timing Characteristics
    21. 6.21 Synchronous Type 2 Card Activation Timing Characteristics
    22. 6.22 Card Deactivation Timing Characteristics
    23. 6.23 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Card Interface Modules
      2. 8.3.2 SAM Card Interface Modules
      3. 8.3.3 User Card Interface Module
      4. 8.3.4 Clock Division and Multiplexing
      5. 8.3.5 IO Multiplexing
      6. 8.3.6 GPIO Operation
      7. 8.3.7 Power Management Features
      8. 8.3.8 ESD Protection
      9. 8.3.9 I2C interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Off Mode
      2. 8.4.2  Shutdown Mode
      3. 8.4.3  Standby Mode
      4. 8.4.4  Active Mode
        1. 8.4.4.1 User Card Operating Mode Selection
        2. 8.4.4.2 Synchronous Type 1 Operating Mode
        3. 8.4.4.3 Synchronous Type 2 Operating Mode
        4. 8.4.4.4 Manual Operating Mode
        5. 8.4.4.5 Asynchronous Operating Mode
        6. 8.4.4.6 Warm Reset Sequence
        7. 8.4.4.7 Deactivation Sequence
      5. 8.4.5  User Card Insertion / Removal Detection
      6. 8.4.6  IO Operation
        1. 8.4.6.1 IO Switching Control
        2. 8.4.6.2 IO Rise Time and Fall Time control
        3. 8.4.6.3 Current Limiting on IO Pin
      7. 8.4.7  CLK Operation
        1. 8.4.7.1 CLK Switching
        2. 8.4.7.2 CLK Rise Time and Fall Time Control
        3. 8.4.7.3 Current Limiting On CLK Pin
      8. 8.4.8  RST Operation
        1. 8.4.8.1 Current Limiting On RST
      9. 8.4.9  Interrupt Operation
        1. 8.4.9.1  Card Insertion And Removal
        2. 8.4.9.2  Over Current Fault
        3. 8.4.9.3  Supervisor Fault
        4. 8.4.9.4  Over Temperature Fault
        5. 8.4.9.5  EARLY Fault
        6. 8.4.9.6  MUTE Fault
        7. 8.4.9.7  Synchronous Activation Complete
        8. 8.4.9.8  VCC Ramp Fault
        9. 8.4.9.9  GPIO Input State Transition
        10. 8.4.9.10 POR Interrupt
      10. 8.4.10 Power Management
        1. 8.4.10.1 Voltage Supervisor
        2. 8.4.10.2 DC-DC Boost
        3. 8.4.10.3 LDOs and Load Transient Response
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Operation
        1. 8.5.1.1 I2C Read and Write Procedures
        2. 8.5.1.2 I2C Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Memory Map
        1. Table 12. 91
        2. Table 13. 92
        3. Table 14. 93
        4. Table 15. 94
        5. Table 16. 95
        6. Table 17. 96
        7. Table 18. 97
        8. Table 19. 98
        9. Table 20. 99
        10. Table 21. 100
        11. Table 22. 101
        12. Table 23. 102
        13. Table 24. 103
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IO Pin Fall Time Setting
        2. 9.2.2.2 CLK Pin Rise Time And Fall Time Settings
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On-Reset
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DC-DC Boost Layout Recommendation
      2. 11.1.2 Card Interface Layout Recommendations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 商标
    2. 12.2 静电放电警告
    3. 12.3 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.1 Memory Map

Address (Hex) Register Description Type Reset (Hex) Reset (Binary) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 User Card Interface Status R 00 0000 0000 ACTIVE_UC EARLY_UC MUTE_UC PROT_UC CLKSW_UC PRESL_UC PRES_UC VCC_FAIL_UC
01 User Card Interface Settings R/W 60 0110 0000 SET_VCC_UC IO_EN_UC WARM_UC CARD_DETECT_UC START_ASYNC_UC
02 User Card Clock Settings R/W 0C 0000 1100 INTERN_CLK_UC CLK0_UC CLK1_UC CLK_DIV_UC
03 Asynchronous Mode ATR EARLY Counter MSB for User Card R/W AA 1010 1010 EARLY_COUNT_HI_UC
04 Asynchronous Mode ATR EARLY Counter LSB for User Card R/W 00 0000 0000 EARLY_COUNT_LO_UC
05 Asynchronous Mode ATR MUTE Counter MSB for User Card R/W A4 1010 0100 MUTE_COUNT_HI_UC
06 Asynchronous Mode ATR MUTE Counter LSB for User Card R/W 74 0111 0100 MUTE_COUNT_LO_UC
07 User Card IO Slew Rate Settings R/W 80 1000 0000 IO_TR_UC IO_TF_UC
08 User Card Clock Slew Rate Settings R/W A0 1010 0000 CLK_SR_UC
09 User Card Synchronous Mode Settings R/W 76 0111 0110 CARD_TYPE ACTIVATION_TYPE C4 C8 RST CLK_ENABLE_SYNC EDGE START_SYNC
0A Synchronous Mode ATR Byte 1 R 00 0000 0000 BYTE1_UC
0B Synchronous Mode ATR Byte 2 R 00 0000 0000 BYTE2_UC
0C Synchronous Mode ATR Byte 3 R 00 0000 0000 BYTE3_UC
0D Synchronous Mode ATR Byte 4 R 00 0000 0000 BYTE4_UC
10 SAM1 Interface Status R 00 0000 0000 ACTIVE_SAM1 EARLY_SAM1 MUTE_SAM1 PROT_SAM1 CLKSW_SAM1 STAT_OTP STAT_SUPL VCC_FAIL_SAM1
11 SAM1 Interface Settings R/W 40 0100 0000 SET_VCC_SAM1 IO_EN_SAM1 WARM_SAM1 START_ASYNC_SAM1
12 SAM1 Clock Settings R/W 0C 0000 1100 INTERN_CLK_SAM1 CLK0_SAM1 CLK1_SAM1 CLK_DIV_SAM1
13 Asynchronous Mode ATR EARLY Counter MSB for SAM1 R/W AA 1010 1010 EARLY_COUNT_HI_SAM1
14 Asynchronous Mode ATR EARLY Counter LSB for SAM1 R/W 00 0000 0000 EARLY_COUNT_LO_SAM1
15 Asynchronous Mode ATR MUTE Counter MSB for SAM1 R/W A4 1010 0100 MUTE_COUNT_HI_SAM1
16 Asynchronous Mode ATR MUTE Counter LSB for SAM1 R/W 74 0111 0100 MUTE_COUNT_LO_SAM1
17 SAM IO Slew Rate Settings R/W 80 1000 0000 IO_TR_SAM IO_TF_SAM
18 SAM Clock Slew Rate Settings R/W A0 1010 0000 CLK_SR_SAM
20 SAM2 Interface Status R 00 0000 0000 ACTIVE_SAM2 EARLY_SAM2 MUTE_SAM2 PROT_SAM2 CLKSW_SAM2 VCC_FAIL_SAM2
21 SAM2 Interface Settings R/W 40 0100 0000 SET_VCC_SAM2 IO_EN_SAM2 WARM_SAM2 START_ASYNC_SAM2
22 SAM2 Clock Settings R/W 0C 0000 1100 INTERN_CLK_SAM2 CLK0_SAM2 CLK1_SAM2 CLK_DIV_SAM2
23 Asynchronous Mode ATR EARLY Counter MSB for SAM2 R/W AA 1010 1010 EARLY_COUNT_HI_SAM2
24 Asynchronous Mode ATR EARLY Counter LSB for SAM2 R/W 00 0000 0000 EARLY_COUNT_LO_SAM2
25 Asynchronous Mode ATR MUTE Counter MSB for SAM2 R/W A4 1010 0100 MUTE_COUNT_HI_SAM2
26 Asynchronous Mode ATR MUTE Counter LSB for SAM2 R/W 74 0111 0100 MUTE_COUNT_LO_SAM2
30 SAM3 Interface Status R 00 0000 0000 ACTIVE_SAM3 EARLY_SAM3 MUTE_SAM3 PROT_SAM3 CLKSW_SAM3 VCC_FAIL_SAM3
31 SAM3 Interface Settings R/W 40 0100 0000 SET_VCC_SAM3 IO_EN_SAM3 WARM_SAM3 START_ASYNC_SAM3
32 SAM3 Clock Settings R/W 0C 0000 1100 INTERN_CLK_SAM3 CLK0_SAM3 CLK1_SAM3 CLK_DIV_SAM3
33 Asynchronous Mode ATR EARLY Counter MSB for SAM3 R/W AA 1010 1010 EARLY_COUNT_HI_SAM3
34 Asynchronous Mode ATR EARLY Counter LSB for SAM3 R/W 00 0000 0000 EARLY_COUNT_LO_SAM3
35 Asynchronous Mode ATR MUTE Counter MSB for SAM3 R/W A4 1010 0100 MUTE_COUNT_HI_SAM3
36 Asynchronous Mode ATR MUTE Counter LSB for SAM3 R/W 74 0111 0100 MUTE_COUNT_LO_SAM3
40 Product Version R 00 0000 0000 PRODUCT_VER
41 Interrupt Status Register R 00 0000 0000 INT_UC INT_SAM1 INT_SAM2 INT_SAM3 INT_OTP INT_SUPL INT_SYNC_COMPLETE INT_GPIO
42 Device Settings R/W 80 1000 0000 DC_DC GPIO4 GPIO3 GPIO2 GPIO1
43 GPIO Settings R/W xF xxxx 1111 GPIO4_INPUT GPIO3_INPUT GPIO2_INPUT GPIO1_INPUT GPIO4_OUTPUT GPIO3_OUTPUT GPIO2_OUTPUT GPIO1_OUTPUT
44 User Card Interrupt Mask Register R/W 00 0000 0000 EARLY_UC_ MASK MUTE_UC_ MASK PROT_UC_ MASK SYNC_COMPLETE_MASK OTP_MASK SUPL_MASK GPIO_INT_ MASK PRESL_INT_ MASK
45 SAM1 and SAM2 Interrupt Mask Register R/W 00 0000 0000 EARLY_SAM1_MASK MUTE_SAM1_MASK PROT_SAM1_MASK EARLY_SAM2_MASK MUTE_SAM2_MASK PROT_SAM2 _MASK VCC_FAIL_SAM_MASK VCC_FAIL_UC_ MASK
46 SAM3 and GPIO Interrupt Mask Register R/W 00 0000 0000 EARLY_SAM3_MASK MUTE_SAM3_MASK PROT_SAM3_MASK GPIO4_INT_MASK GPIO3_INT_MASK GPIO2_INT_MASK GPIO1_INT_ MASK

Table 12.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x00 User Card Interface Status
0x00 1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive		 ACTIVE_UC 7 R 1'b0
0x00 1: Indicates card ATR was received before the ATR valid window. INT_UC bit is set in interrupt register.
Bit is cleared when the register is read		 EARLY_UC 6 R 1'b0
0x00 1: Indicates card ATR was not received within the ATR valid window. INT_UC bit is set in interrupt register. Bit is cleared when the register is read. MUTE_UC 5 R 1'b0
0x00 1: Indicates over current condition on the card interface. INT_UC bit is set in interrupt register.
Bit clears when the register is read		 PROT_UC 4 R 1'b0
0x00 1: Indicates the card interface is in internal CLK mode i.e frequency on CLK pin is ~1.2 Mhz
0: Indicates the card interface is not in internal clock mode.		 CLKSW_UC 3 R 1'b0
0x00 1: indicates the card has been inserted or extracted. INT_UC bit is set in interrupt register.
Bit is cleared when the register is read		 PRESL_UC 2 R 1'b0
0x00 1: indicates a card is present
0: indicates a card is not present		 PRES_UC 1 R 1'b0
0x00 1: indicates VCC ramp fault on card interface. INT_UC bit is set in interrupt register.
Bit is cleared when register is read		 VCC_FAIL_UC 0 R 1’b0

Table 13.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x01 User Card Interface Settings
0x01 00 : set VCC to 1.8 V
01 : set VCC to 1.8 V
10 : set VCC to 3 V
11 : set VCC to 5 V		 SET_VCC_UC [7:6] R/W 2'b01
0x01 1: IOMC1 is connected IOUC
0: IOMC1 is disconnected from IOUC		 IO_EN_UC 5 R/W 1'b1
0x01 1: Warm reset sequence is started on user card interface
Bit is clears when warm reset sequence starts.
Bit is ignored if card interface is in synchronous type 1 operating mode, synchronous type 2 operating mode or manual operating mode. 		WARM_UC 3 R/W 1'b0
0x01 1 :Low to high transition on PRES pin indicates card insertion
0 : High to low transition on PRES pin indicates card insertion		 CARD_DETECT_UC 2 R/W 1'b0
0x01 1: Starts asynchronous activation sequence
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs
Bit is ignored if card interface is in synchronous type 1 operating mode, synchronous type 2 operating mode or manual operating mode. 		START_ASYNC_UC 0 R/W 1'b0

Table 14.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x02 User Card Clock Settings
0x02 In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to ~1.2 MHz
0: CLKUC is set by Bit[6] or Bit[5] or Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
Bit is ignored in Sync mode		 INTERN_CLK_UC 7 R/W 1'b0
0x02 In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to 0
0: CLKUC is set by Bit[5] or Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
1: CLKUC is set to 0
0: CLKUC is set by Bit5.		 CLK0_UC 6 R/W 1'b0
0x02 In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to 1
0: CLKUC is set by Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
Usable only is CLK_ENABLE_SYNC=0
1: CLKUC is set to 1
0: CLKUC is set to 1		 CLK1_UC 5 R/W 1'b0
0x02 In asynchronous operating mode
(START_ASYNC=1)
000: CLKUC frequency = CLKIN1
001: CLKUC frequency = CLKIN1/2.
010: CLKUC frequency = CLKIN1/4.
011: CLKUC frequency = CLKIN1/5.
100: CLKUC frequency = CLKIN1/8.
101: CLKUC frequency = CLKIN1/8.
110: CLKUC frequency = CLKIN1/8.
111: CLKUC frequency = CLKIN1/8.
In synchronous operating mode
(START_SYNC=1)
Usable only is CLK_ENABLE_SYNC=1
[111:000] : CLKUC = CLKIN1		 CLK_DIV_UC [4:2] R/W 3'b011
0x03 Asynchronous Mode ATR EARLY Counter MSB for User Card
0x03 MSB (8-bits) of programmable 10-bit clock counter value. EARLY_COUNT_HI_UC [7:0] R/W 8'b10101010
0x04 Asynchronous Mode ATR EARLY Counter LSB for User Card
0x04 LSB (2-bits) of programmable 10-bit clock counter value. EARLY_COUNT_LO_UC [7:6] R/W 2'b00
0x05 Asynchronous Mode ATR MUTE Counter MSB for User Card
0x05 MSB (8-bits) of programmable 16-Bit clock counter value. MUTE_COUNT_HI_UC [7:0] R/W 8'b10100100
0x06 Asynchronous Mode ATR MUTE Counter LSB for User Card
0x06 LSB (8-bits) of programmable 16-Bit clock counter value. MUTE_COUNT_LO_UC [7:0] R/W 8'b01110100
0x07 User Card IO Slew Rate Settings
0x07 3 Bit value defining the rise time of IOUC IO_TR_UC [7:5] R/W 3'b100
0x07 2 Bit value defining the fall time of IOUC IO_TF_UC [4:3] R/W 2'b00
0x08 User Card Clock Slew Rate Settings
0x08 4 Bit value defining the rise time and fall time of the CLKUC CLK_SR_UC [7:4] R/W 4'b1010

Table 15.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x09 User Card Synchronous Mode Settings
0x09 0: Synchronous Type 1 card activation is selected
1: Synchronous Type 2 card activation is selected		 CARD_TYPE 7 R/W 1'b0
0x09 1: Automatic activation per bit[7] is selected
0: Manual operating mode is selected		 ACTIVATION_TYPE 6 R/W 1'b1
0x09 0 :Llow level is driven on C4 or C4 is being driven low externally
1 : C4 is pulled up high by internal pull-up Bit has no effect if card interface is not active 		C4 5 R/W 1'b1
0x09 0 : Low level is driven on C8 or C8 is being driven low externally
1 : C8 is pulled up high by internal pull-up Bit has no effect if card interface is not active 		C8 4 R/W 1'b1
0x09 0 : Low level is driven on RSTUC
1 : High level is driven on RSTUC
Bit has no effect when card interface is not active.
Bit has no effect if card interface is activated in asynchronous operating mode 		RST 3 R/W 1'b0
0x09 0 : CLKUC is driven low or high based on the clock settings register (Reg 0x02, Bit [6:5])
1 : CLK output is controlled by CLKIN1
Bit has no effect when card interface is not active.
Bit has no effect if card interface is activated in asynchronous operating mode 		CLK_ENABLE_SYNC 2 R/W 1'b1
0x09 1 : IO line is sampled on rising edge during synchronous type 1 activation sequence
0 : IO line sampled on falling edge during synchronous type 1 activation sequence
Bit has no effect when card interface is not active.
Bit has no effect if card interface is activated in asynchronous operating mode 		EDGE 1 R/W 1'b1
0x09 1 : Start card interface activation based on bit[7:6]
0: Start deactivation sequence bit clears when automatic deactivation occurs. 		START_SYNC 0 R/W 1'b0
REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x0A Synchronous Mode ATR Byte1
0x0A Bit 7 to Bit 0 of ATR response BYTE1_UC [7:0] R 8'b00000000
0x0B Synchronous Mode ATR Byte2
0x0B Bit 15 to Bit 8 of ATR response BYTE2_UC [7:0] R 8'b00000000
0x0C Synchronous Mode ATR Byte3
0x0C Bit 23 to Bit 16 of ATR response BYTE3_UC [7:0] R 8'b00000000
0x0D Synchronous Mode ATR Byte4
0x0D Bit 31 to Bit 24 of ATR response BYTE4_UC [7:0] R 8'b00000000

Table 16.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x10 SAM1 Interface Status
0x10 1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive 		ACTIVE_SAM1 7 R 1'b0
0x10 1: Indicates card ATR was received before the ATR valid window. INT_SAM1 bit is set in interrupt register.
Bit is cleared when the register is read		 EARLY_SAM1 6 R 1'b0
0x10 1: Indicates card ATR was not received within the ATR valid window. INT_SAM1 bit is set in interrupt register. Bit is cleared when the register is read. MUTE_SAM1 5 R 1'b0
0x10 1: Indicates over current condition on the card interface. INT_SAM1 bit is set in interrupt register. Bit clears when the register is read PROT_UC_SAM1 4 R 1'b0
0x10 1: Indicates the card interface is in internal CLK mode i.e frequency on CLK pin is ~1.2 Mhz
0: Indicates the card interface is not in internal clock mode.		 CLKSW_SAM1 3 R 1'b0
0x10 1: Indicates that an over temperature fault condition exists
0: Over temperature fault doesn’t exist		 STAT_OTP 2 R 1'b0
0x10 1: Indicates a supervisor fault condition exists.
0: Supervisor fault condition doesn’t exist.		 STAT_SUPL 1 R 1'b0
0x10 1: Indicates VCC ramp fault on card interface.
INT_SAM1 bit is set in interrupt register.
Bit is cleared when register is read		 VCC_FAIL_SAM1 0 R 1’b0
0x11 SAM1 Interface Settings
0x11 00 : Set VCC to 1.8 V
01 : Set VCC to 1.8 V
10 : Set VCC to 3 V
11 : Set VCC to 5 V		 SET_VCC_SAM1 [7:6] R/W 2'b01
0x11 1: IOMC2 is connected to IOS1
0: IOMC2 is disconnected from IOS1		 IO_EN_SAM1 5 R/W 1'b0
0x11 1: Warm reset sequence is started on SAM1
Bit is clears when warm reset sequence starts.		 WARM_SAM1 3 R/W 1'b0
0x11 1: Starts activation sequence
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs		 START_ASYNC_SAM1 0 R/W 1'b0
REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x12 SAM1 Clock Settings
0x12 1 : Card CLK is set to ~1.2 MHz
0 : Card CLK is set by Bit[6], Bit[5] or Bit[4:2]		 INTERN_CLK_SAM1 7 R/W 1'b0
0x12 1 : Card CLK is set to 0
0 : Card CLK is set by Bit[5] or Bit[4:2]		 CLK0_SAM1 6 R/W 1'b0
0x12 1 : Card CLK is set to 1
0 : Card CLK is set by Bit[4:2]		 CLK1_SAM1 5 R/W 1'b0
0x12 000 : CLKS1 frequency = CLKIN2
001 : CLKS1 frequency = CLKIN2/2
010 : CLKS1 frequency = CLKIN2/4
011 : CLKS1 frequency = CLKIN2/5
100: CLKS1 frequency = CLKIN2/8
101: CLKS1 frequency = CLKIN2/8
110: CLKS1 frequency = CLKIN2/8
111: CLKS1 frequency = CLKIN2/8		 CLK_DIV_SAM1 [4:2] R/W 3'b011
0x13 Asynchronous Mode ATR EARLY Counter MSB for SAM1
0x13 MSB (8-bits) of programmable 10-bit clock counter value EARLY_COUNT_HI_SAM1 [7:0] R/W 8'b10101010
0x14 Asynchronous Mode ATR EARLY Counter LSB for SAM1
0x14 LSB (2-bits) of programmable 10-bit clock counter value EARLY_COUNT_LO_SAM1 [7:6] R/W 2'b00

Table 17.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x15 Asynchronous Mode ATR MUTE counter MSB for SAM1
0x15 MSB (8-bits) of programmable 16-bit clock counter value MUTE_COUNT_HI_SAM1 [7:0] R/W 8'b10100100
0x16 Asynchronous Mode ATR MUTE counter LSB for SAM1
0x16 MSB (8-bits) of programmable 16-bit clock counter value MUTE_COUNT_LO_SAM1 [7:0] R/W 8'b01110100
0x17 SAM IO Slew Rate Settings
0x17 3-Bit value defining the rise time of IO pin for all SAM interfaces IO_TR_SAM [7:5] R/W 3'b100
0x17 2-Bit value defining the rise time of IO pin for all SAM interfaces IO_TF_SAM [4:3] R/W 2'b00
0x18 SAM Clock Slew Rate Settings
0x18 4-Bit value defining the rise time and fall time of CLK for all SAM interfaces CLK_SR_SAM1 [7:4] R/W 4'b1010

Table 18.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x20 SAM2 Interface Status
0x20 1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive 		ACTIVE_SAM2 7 R 1'b0
0x20 1: Indicates card ATR was received before the ATR valid window. INT_SAM2 bit is set in interrupt register.
Bit is cleared when the register is read		 EARLY_SAM2 6 R 1'b0
0x20 1: Indicates card ATR was not received within the ATR valid window. INT_SAM2 bit is set in interrupt register.
Bit is cleared when the register is read.		 MUTE_SAM2 5 R 1'b0
0x20 1: Indicates over current condition on the card interface. INT_SAM2 bit is set in interrupt register.
Bit clears when the register is read		 PROT_UC_SAM2 4 R 1'b0
0x20 1: Indicates the card interface is in internal CLK mode i.e frequency on CLK pin is ~1.2Mhz
0: Indicates the card interface is not in internal clock mode.		 CLKSW_SAM2 3 R 1'b0
0x20 1: indicates VCC ramp fault on card interface. INT_SAM2 bit is set in interrupt register.
Bit is cleared when register is read		 VCC_FAIL_SAM2 0 R 1’b0
0x21 SAM2 Interface Settings
0x21 00 : set VCC to 1.8 V
01 : set VCC to 1.8 V
10 : set VCC to 3 V
11 : set VCC to 5 V		 SET_VCC_SAM2 [7:6] R/W 2'b01
0x21 1: IOMC2 is connected to IOS2
0: IOMC2 is disconnected from IOS2		 IO_EN_SAM2 5 R/W 1'b0
0x21 1: Warm reset sequence is started on SAM2
Bit is clears when warm reset sequence starts.		 WARM_SAM2 3 R/W 1'b0
0x21 1: Starts activation sequence
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs		 START_ASYNC_SAM2 0 R/W 1'b0

Table 19.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x22 SAM2 Clock Settings
0x22 1 : Card CLK is set to ~1.2MHz
0 : CLKS2 is set by Bit[6] or Bit [5] or Bit[4:2]		 INTERN_CLK_SAM2 7 R/W 1'b0
0x22 1 : Card CLK is set to 0
0 : CLKS2 is set by Bit[5] or Bit[4:2]		 CLK0_SAM2 6 R/W 1'b0
0x22 1 : Card CLK is set to 1
0 : CLKS2 is set by Bit[4:2]		 CLK1_SAM2 5 R/W 1'b0
0x22 000 : CLKS2 frequency = CLKIN2
001 : CLKS2 frequency = CLKIN2/2
010 : CLKS2 frequency = CLKIN2/4
011 : CLKS2 frequency = CLKIN2/5
100: CLKS2 frequency = CLKIN2/8
101: CLKS2 frequency = CLKIN2/8
110: CLKS2 frequency = CLKIN2/8
111: CLKS2 frequency = CLKIN2/8		 CLK_DIV_SAM2 [4:2] R/W 3'b011
0x23 Asynchronous Mode ATR EARLY Counter MSB for SAM2
0x23 MSB (8-bits) of programmable 10-bit clock counter value. EARLY_COUNT_HI_SAM2 [7:0] R/W 8'b10101010
0x24 Asynchronous Mode ATR EARLY Counter LSB for SAM2
0x24 LSB (2-bits) of programmable 10-bit clock counter value. EARLY_COUNT_LO_SAM2 [7:6] R/W 2'b00
0x25 Asynchronous Mode ATR MUTE Counter MSB for SAM2
0x25 MSB (8-bits) of programmable 16-bit clock counter value. MUTE_COUNT_HI_SAM2 [7:0] R/W 8'b10100100
0x26 Asynchronous Mode ATR MUTE Counter LSB for SAM2
0x26 MSB (8-bits) of programmable 16-bit clock counter value. MUTE_COUNT_LO_SAM2 [7:0] R/W 8'b01110100

Table 20.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x30 SAM3 Interface Status
0x30 1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive 		ACTIVE_SAM3 7 R 1'b0
0x30 1: Indicates card ATR was received before the ATR valid window. INT_SAM3 bit is set in interrupt register.
Bit is cleared when the register is read		 EARLY_SAM3 6 R 1'b0
0x30 1: Indicates card ATR was not received within the ATR valid window. INT_SAM3 bit is set in interrupt register.
Bit is cleared when the register is read.		 MUTE_SAM3 5 R 1'b0
0x30 1: Indicates over current condition on the card interface. INT_SAM3 bit is set in interrupt register
Bit clears when the register is read		 PROT_UC_SAM3 4 R 1'b0
0x30 1: Indicates the card interface is in internal CLK mode i.e frequency on CLK pin is ~1.2Mhz
0: Indicates the card interface is not in internal clock mode.		 CLKSW_SAM3 3 R 1'b0
0x30 1: Indicates VCC ramp fault on card interface. INT_SAM3 bit is set in interrupt register.
Bit is cleared when register is read		 VCC_FAIL_SAM3 0 R 1’b0
0x31 SAM3 Interface Settings
0x31 00 : set VCC to 1.8 V
01 : set VCC to 1.8 V
10 : set VCC to 3V
11 : set VCC to 5V		 SET_VCC_SAM3 [7:6] R/W 2'b01
0x31 1: IOMC2 is connected to IOS3
0: IOMC2 is disconnected from IOS3		 IO_EN_SAM3 5 R/W 1'b0
0x31 1: Warm reset sequence is started on SAM3
Bit is clears when warm reset sequence starts.		 WARM_SAM3 3 R/W 1'b0
0x31 1: Starts activation sequence
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs		 START_ASYNC_SAM3 0 R/W 1'b0

Table 21.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x32 SAM3 Clock Settings
0x32 1 : CLKS3 is set to ~1.2 Mhz
0 : CLKS3 is set by Bit[6] or Bit [5] or Bit[4:2]		 INTERN_CLK_SAM3 7 R/W 1'b0
0x32 1 : CLKS3 is set to 0
0 : CLKS3 is set by Bit[5] or Bit[4:2]		 CLK0_SAM3 6 R/W 1'b0
0x32 1 : CLKS3 is set to 1
0 : CLKS3 is set by Bit[4:2]		 CLK1_SAM3 5 R/W 1'b0
0x32 000 : CLKS3 frequency = CLKIN2
001 : CLKS3 frequency = CLKIN2/2
010 : CLKS3 frequency = CLKIN2/4
011 : CLKS3 frequency = CLKIN2/5
100: CLKS3 frequency = CLKIN2/8
101: CLKS3 frequency = CLKIN2/8
110: CLKS3 frequency = CLKIN2/8
111: CLKS3 frequency = CLKIN2/8		 CLK_DIV_SAM3 [4:2] R/W 3'b011
0x33 Asynchronous Mode ATR EARLY Counter MSB for SAM3
0x33 MSB (8-bits) of programmable 10-bit clock counter value. EARLY_COUNT_HI_SAM3 [7:0] R/W 8'b10101010
0x34 Asynchronous Mode ATR EARLY Counter LSB for SAM3
0x34 LSB (2-bits) of programmable 10-bit clock counter value. EARLY_COUNT_LO_SAM3 [7:6] R/W 2'b00
0x35 Asynchronous Mode ATR MUTE Counter MSB for SAM3
0x35 MSB (8-bits) of programmable 16-bit clock counter value. MUTE_COUNT_HI_SAM3 [7:0] R/W 8'b10100100
0x36 Asynchronous Mode ATR MUTE Counter LSB for SAM3
0x36 MSB (8-bits) of programmable 16-bit clock counter value. [7:0] R/W 8'b01110100

Table 22.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x40 Product Version
0x40 Product Version PRODUCT_VER [7:0] R 8'b00000000
0x41 Interrupt Status Register
0x41 1: PROT, MUTE, EARLY, VCC_FAIL or PRESL bit set in User card. INT pin is asserted low when this bit is set.
0 : Bit clears when Register is read		 INT_UC 7 R 1'b0
0x41 1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM1. INT is asserted low when this bit is set.
0 : Bit clears when Register is read		 INT_SAM1 6 R 1'b0
0x41 1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM2. INT is asserted low when this bit is set.
0 : Bit clears when Register is read		 INT_SAM2 5 R 1'b0
0x41 1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM3. INT is asserted low when this bit is set.
0 : Bit clears when Register is read		 INT_SAM3 4 R 1'b0
0x41 1: All card interfaces deactivated due to over temperature fault. INT is asserted low when this bit is set.
0 : Bit clears when Register is read		 INT_OTP 3 R 1'b0
0x41 1: All card interfaces deactivated due to Supervisor fault. INT is asserted low when this bit is set.
0 : Bit clears when register is read		 INT_SUPL 2 R 1'b0
0x41 1: Sync card activation sequence complete. INT is asserted low when this bit is set.
0 : Bit clears when register is read		 INT_SYNC_COMPLETE 1 R 1'b0
0x41 1: One of the GPIO inputs has changes state. INT is asserted low when this bit is set.
0 : Bit clears when register is read		 INT_GPIO 0 R 1'b0
0x42 Device Settings
0x42 1: DC-DC boost is enabled
0: DC-DC boost is disabled		 DC_DC 7 R/W 1'b1
0x42 1: GPIO4 is configured as input
0: GPIO4 is configured as output		 GPIO4 5 R/W 1'b0
0x42 1: GPIO3 is configured as input
0: GPIO3 is configured as output		 GPIO3 4 R/W 1'b0
0x42 1: GPIO2 is configured as input
0: GPIO2 is configured as output		 GPIO2 3 R/W 1'b0
0x42 1: GPIO1 is configured as input
0: GPIO1 is configured as output		 GPIO1 2 R/W 1'b0

Table 23.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x43 GPIO Settings
0x43 Reflects level on GPIO4 (read only) GPIO4_INPUT 7 R 1'b0
0x43 Reflects level on GPIO3 (read only) GPIO3_INPUT 6 R 1'b0
0x43 Reflects level on GPIO2 (read only) GPIO2_INPUT 5 R 1'b0
0x43 Reflects level on GPIO1 (read only) GPIO1_INPUT 4 R 1'b0
0x43 Sets level on GPIO4 (Bit is ignored if pin is configured as input) GPIO4_OUTPUT 3 R/W 1'b1
0x43 Sets level on GPIO3 (Bit is ignored if pin is configured as input) GPIO3_OUTPUT 2 R/W 1'b1
0x43 Sets level on GPIO2 (Bit is ignored if pin is configured as input) GPIO2_OUTPUT 1 R/W 1'b1
0x43 Sets level on GPIO1 (Bit is ignored if pin is configured as input) GPIO1_OUTPUT 0 R/W 1'b1
0x44 User Card Interrupt Mask Register
0x44 1: Mask User card EARLY Interrupt
0: Unmask User card EARLY interrupt		 EARLY_UC_MASK 7 R/W 1'b0
0x44 1: Mask User Card MUTE Interrupt
0: Unmask User Card MUTE interrupt		 MUTE_UC _MASK 6 R/W 1'b0
0x44 1: Mask User Card PROT Interrupt
0: Unmask User Card PROT interrupt		 PROT_UC_MASK 5 R/W 1'b0
0x44 1: Mask sync card activation complete Interrupt
0: Unmask sync card activation complete interrupt		 SYNC_COMPLETE_MASK 4 R/W 1'b0
0x44 1: Mask thermal shutdown Interrupt
0: Unmask thermal shutdown interrupt		 OTP_MASK 3 R/W 1'b0
0x44 1: Mask supervisor fault Interrupt
0: Unmask supervisor fault interrupt		 SUPL_MASK 2 R/W 1'b0
0x44 1: Mask all GPIO Interrupt
0: Unmask all GPIO interrupt		 GPIO_INT_MASK 1 R/W 1'b0
0x44 1: Mask PRESL Interrupt
0: Unmask PRESL interrupt		 PRESL_INT_MASK 0 R/W 1'b0

Table 24.

REGISTER ADDRESS DESCRIPTION FIELD NAME BIT R/W DEFAULT
0x45 SAM1 and SAM2 Interrupt Mask Register
0x45 1: Mask SAM1 EARLY Interrupt
0: Unmask SAM1 EARLY interrupt		 EARLY_SAM1_MASK 7 R/W 1'b0
0x45 1: Mask SAM1 MUTE Interrupt
0: Unmask SAM1 MUTE interrupt		 MUTE_SAM1 _MASK 6 R/W 1'b0
0x45 1: Mask SAM1 PROT Interrupt
0: Unmask SAM1 PROT interrupt		 PROT_SAM1_MASK 5 R/W 1'b0
0x45 1: Mask SAM2 EARLY Interrupt
0: Unmask SAM2 EARLY interrupt		 EARLY_SAM2_MASK 4 R/W 1'b0
0x45 1: Mask SAM2 MUTE Interrupt
0: Unmask SAM2 MUTE interrupt		 MUTE_SAM2 _MASK 3 R/W 1'b0
0x45 1: Mask SAM2 PROT Interrupt
0: Unmask SAM2 PROT interrupt		 PROT_SAM2_MASK 2 R/W 1'b0
0x45 1: Mask VCC_FAIL Interrupt on all SAMs
0: Unmask VCC_FAIL Interrupt on all SAMs		 VCC_FAIL_SAM_MASK 1 R/W 1'b0
0x45 1: Mask VCC_FAIL Interrupt on all User Card
0: Unmask VCC_FAIL Interrupt on all User Card		 VCC_FAIL_UC_MASK 0 R/W 1'b0
0x46 SAM3 and GPIO Interrupt Mask Register
0x46 1: Mask SAM3 EARLY Interrupt
0: Unmask SAM3 EARLY interrupt		 EARLY_SAM3_MASK 7 R/W 1'b0
0x46 1: Mask SAM3 MUTE Interrupt
0: Unmask SAM3 MUTE interrupt		 MUTE_SAM3 _MASK 6 R/W 1'b0
0x46 1: Mask SAM3 PROT Interrupt
0: Unmask SAM3 PROT interrupt		 PROT_SAM3_MASK 5 R/W 1'b0
0x46 1: Mask GPIO4 Interrupt
0: Unmask GPIO4 interrupt		 GPIO4_INT_MASK 4 R/W 1'b0
0x46 1: Mask GPIO3 Interrupt
0: Unmask GPIO3 interrupt		 GPIO3_INT_MASK 3 R/W 1'b0
0x46 1: Mask GPIO2 Interrupt
0: Unmask GPIO2 interrupt		 GPIO2_INT_MASK 2 R/W 1'b0
0x46 1: Mask GPIO1 Interrupt
0: Unmask GPIO1 interrupt		 GPIO1_INT_MASK 1 R/W 1'b0