ZHCSCU3C January   2014  – September 2019 TCA5013

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics—Power Supply and ESD
    6. 6.6  Electrical Characteristics—Card VCC
    7. 6.7  Electrical Characteristics—Card RST
    8. 6.8  Electrical Characteristics—Card CLK
    9. 6.9  Electrical Characteristics—Card Interface IO, C4 and C8
    10. 6.10 Electrical Characteristics—PRES
    11. 6.11 Electrical Characteristics—IOMC1 and IOMC2
    12. 6.12 Electrical Characteristics—CLKIN1 and CLKIN2
    13. 6.13 Electrical Characteristics—A0 and SHDN
    14. 6.14 Electrical Characteristics—INT
    15. 6.15 Electrical Characteristics—GPIO
    16. 6.16 Electrical Characteristics—SDA and SCL
    17. 6.17 Electrical Characteristics—Fault Condition Detection
    18. 6.18 I2C Interface Timing Requirements
    19. 6.19 I2C Interface Timing Characteristics
    20. 6.20 Synchronous Type 1 Card Activation Timing Characteristics
    21. 6.21 Synchronous Type 2 Card Activation Timing Characteristics
    22. 6.22 Card Deactivation Timing Characteristics
    23. 6.23 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Card Interface Modules
      2. 8.3.2 SAM Card Interface Modules
      3. 8.3.3 User Card Interface Module
      4. 8.3.4 Clock Division and Multiplexing
      5. 8.3.5 IO Multiplexing
      6. 8.3.6 GPIO Operation
      7. 8.3.7 Power Management Features
      8. 8.3.8 ESD Protection
      9. 8.3.9 I2C interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Off Mode
      2. 8.4.2  Shutdown Mode
      3. 8.4.3  Standby Mode
      4. 8.4.4  Active Mode
        1. 8.4.4.1 User Card Operating Mode Selection
        2. 8.4.4.2 Synchronous Type 1 Operating Mode
        3. 8.4.4.3 Synchronous Type 2 Operating Mode
        4. 8.4.4.4 Manual Operating Mode
        5. 8.4.4.5 Asynchronous Operating Mode
        6. 8.4.4.6 Warm Reset Sequence
        7. 8.4.4.7 Deactivation Sequence
      5. 8.4.5  User Card Insertion / Removal Detection
      6. 8.4.6  IO Operation
        1. 8.4.6.1 IO Switching Control
        2. 8.4.6.2 IO Rise Time and Fall Time control
        3. 8.4.6.3 Current Limiting on IO Pin
      7. 8.4.7  CLK Operation
        1. 8.4.7.1 CLK Switching
        2. 8.4.7.2 CLK Rise Time and Fall Time Control
        3. 8.4.7.3 Current Limiting On CLK Pin
      8. 8.4.8  RST Operation
        1. 8.4.8.1 Current Limiting On RST
      9. 8.4.9  Interrupt Operation
        1. 8.4.9.1  Card Insertion And Removal
        2. 8.4.9.2  Over Current Fault
        3. 8.4.9.3  Supervisor Fault
        4. 8.4.9.4  Over Temperature Fault
        5. 8.4.9.5  EARLY Fault
        6. 8.4.9.6  MUTE Fault
        7. 8.4.9.7  Synchronous Activation Complete
        8. 8.4.9.8  VCC Ramp Fault
        9. 8.4.9.9  GPIO Input State Transition
        10. 8.4.9.10 POR Interrupt
      10. 8.4.10 Power Management
        1. 8.4.10.1 Voltage Supervisor
        2. 8.4.10.2 DC-DC Boost
        3. 8.4.10.3 LDOs and Load Transient Response
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Operation
        1. 8.5.1.1 I2C Read and Write Procedures
        2. 8.5.1.2 I2C Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Memory Map
        1. Table 12. 91
        2. Table 13. 92
        3. Table 14. 93
        4. Table 15. 94
        5. Table 16. 95
        6. Table 17. 96
        7. Table 18. 97
        8. Table 19. 98
        9. Table 20. 99
        10. Table 21. 100
        11. Table 22. 101
        12. Table 23. 102
        13. Table 24. 103
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IO Pin Fall Time Setting
        2. 9.2.2.2 CLK Pin Rise Time And Fall Time Settings
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On-Reset
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DC-DC Boost Layout Recommendation
      2. 11.1.2 Card Interface Layout Recommendations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 商标
    2. 12.2 静电放电警告
    3. 12.3 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.5.1.1 I2C Read and Write Procedures

Following the successful acknowledgment of the I2C address byte, the bus master shall send one register address byte indicating the address of the register on which the read or write operation needs to be performed. This register address is stored in an internal register and used by the device for subsequent read/write to the device. After the device address is acknowledged by the slave, all register addresses will be acknowledged even if an actual register is not defined for that address

The TCA5013 supports an auto increment feature by which multiple bytes can be written to consecutive registers without requiring the master to send the device address and register address for each data byte. Auto increment is enabled by setting the MSB of the register address to a 1 (see Figure 23). If auto increment is used to write the entire register map, the gaps in the register address map need to be written with dummy bytes. If auto increment is used to read the entire register map then data read from gaps in the register map will be 8’hFF

TCA5013 fig006_SCPS253.gifFigure 23. I2C Write Procedure
TCA5013 fig007_SCPS253.gifFigure 24. I2C Read Procedure
TCA5013 fig008_SCPS253.gifFigure 25. I2C Read Procedure with Repeated Start