ZHCSMQ9B September   2020  – November 2022 SN65MLVD203B

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  绝对最大额定值
    2. 6.2  ESD 等级
    3. 6.3  建议运行条件
    4. 6.4  热性能信息
    5. 6.5  电气特性
    6. 6.6  电气特性 - 驱动器
    7. 6.7  电气特性 - 接收器
    8. 6.8  开关特性 - 驱动器
    9. 6.9  开关特性 - 接收器
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset
      2. 8.3.2 ESD Protection
      3. 8.3.3 RX Maximum Jitter While DE Toggling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VCC < 1.5 V
      2. 8.4.2 Operations with 1.5 V ≤ VCC < 3 V
      3. 8.4.3 Operation with 3 V ≤ VCC < 3.6 V
      4. 8.4.4 Device Function Tables
      5. 8.4.5 Equivalent Input and Output Schematic Diagrams
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1  Supply Voltage
        2. 9.2.3.2  Supply Bypass Capacitance
        3. 9.2.3.3  Driver Input Voltage
        4. 9.2.3.4  Driver Output Voltage
        5. 9.2.3.5  Termination Resistors
        6. 9.2.3.6  Receiver Input Signal
        7. 9.2.3.7  Receiver Input Threshold (Failsafe)
        8. 9.2.3.8  Receiver Output Signal
        9. 9.2.3.9  Interconnecting Media
        10. 9.2.3.10 PCB Transmission Lines
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Microstrip vs. Stripline Topologies
        2. 9.4.1.2 Dielectric Type and Board Construction
        3. 9.4.1.3 Recommended Stack Layout
        4. 9.4.1.4 Separation Between Traces
        5. 9.4.1.5 Crosstalk and Ground Bounce Minimization
        6. 9.4.1.6 Decoupling
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

7 Parameter Measurement Information

GUID-40D1BD7F-6234-4461-B38D-961A44F5ABDF-low.gif Figure 7-1 Driver Voltage and Current Definitions
GUID-BB467C94-825E-4A84-913A-E7BF605880A5-low.gif
A. All resistors are 1% tolerance.
Figure 7-2 Differential Output Voltage Test Circuit
GUID-EB9FC7E1-0B52-40CB-AAFF-A25FA8AEFBD5-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 7-3 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
GUID-937EB00F-BABC-4661-8A8F-A5461BF2100A-low.gif Figure 7-4 Driver Short-Circuit Test Circuit
GUID-2CF97D7E-011F-47B8-8A96-791D865ACBA3-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 7-5 Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
GUID-25404FD6-0619-4E53-8A95-742D05A0C141-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 7-6 Driver Enable and Disable Time Circuit and Definitions
GUID-DE7E75A9-B703-49C1-A593-5D73536ABDE4-low.gif Figure 7-7 Maximum Steady State Output Voltage
GUID-FDE9678A-17EE-49B3-BEC5-AD0E25A824DD-low.gif
A. All input pulses are supplied by an Agilent 81250 Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200 Mbps 215–1 PRBS input.
Figure 7-8 Driver Jitter Measurement Waveforms
GUID-9CAB42DB-1A35-4ED7-889A-ED5CBA9C7CEC-low.gif Figure 7-9 Receiver Voltage and Current Definitions
Table 7-1 Type-1 Receiver Input Threshold Test Voltages
APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE		 RESULTING COMMON-
MODE INPUT VOLTAGE		 RECEIVER
OUTPUT
VIA VIB VID VIC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.425 3.375 0.050 3.4 H
3.375 3.425 –0.050 3.4 L
–0.975 –1.025 0.050 –1 H
–1.025 –0.975 –0.050 –1 L
GUID-E61D328F-22BA-4C07-B52B-AEC0E2349CE4-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 7-10 Receiver Timing Test Circuit and Waveforms
GUID-4EACD7AA-4803-4485-BE73-1D30C945911B-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%.
Figure 7-11 Receiver Enable and Disable Time Test Circuit and Waveforms
GUID-BF83E52D-290C-4A26-9A5C-BCBDB6F2192C-low.gif
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 10 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200 Mbps 215-1 PRBS input.
Figure 7-12 Receiver Jitter Measurement Waveforms