ZHCSMQ9B September   2020  – November 2022 SN65MLVD203B

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  绝对最大额定值
    2. 6.2  ESD 等级
    3. 6.3  建议运行条件
    4. 6.4  热性能信息
    5. 6.5  电气特性
    6. 6.6  电气特性 - 驱动器
    7. 6.7  电气特性 - 接收器
    8. 6.8  开关特性 - 驱动器
    9. 6.9  开关特性 - 接收器
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset
      2. 8.3.2 ESD Protection
      3. 8.3.3 RX Maximum Jitter While DE Toggling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VCC < 1.5 V
      2. 8.4.2 Operations with 1.5 V ≤ VCC < 3 V
      3. 8.4.3 Operation with 3 V ≤ VCC < 3.6 V
      4. 8.4.4 Device Function Tables
      5. 8.4.5 Equivalent Input and Output Schematic Diagrams
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1  Supply Voltage
        2. 9.2.3.2  Supply Bypass Capacitance
        3. 9.2.3.3  Driver Input Voltage
        4. 9.2.3.4  Driver Output Voltage
        5. 9.2.3.5  Termination Resistors
        6. 9.2.3.6  Receiver Input Signal
        7. 9.2.3.7  Receiver Input Threshold (Failsafe)
        8. 9.2.3.8  Receiver Output Signal
        9. 9.2.3.9  Interconnecting Media
        10. 9.2.3.10 PCB Transmission Lines
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Microstrip vs. Stripline Topologies
        2. 9.4.1.2 Dielectric Type and Board Construction
        3. 9.4.1.3 Recommended Stack Layout
        4. 9.4.1.4 Separation Between Traces
        5. 9.4.1.5 Crosstalk and Ground Bounce Minimization
        6. 9.4.1.6 Decoupling
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

9.4.1.3 Recommended Stack Layout

Following the choice of dielectrics and design specifications, you must decide how many levels to use in the stack. To reduce the TTL/CMOS to M-LVDS crosstalk, it is a good practice to have at least two separate signal planes as shown in Figure 9-9.

GUID-211CBDAD-F733-416B-AB0B-999190B85CD9-low.gifFigure 9-9 Four-Layer PCB Board
Note:

The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients.

One of the most common stack configurations is the six-layer board, as shown in Figure 9-10.

GUID-4730438A-50EF-4A31-AED4-9122DD090727-low.gifFigure 9-10 Six-Layer PCB Board

In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.