ZHCSBQ4B September   2013  – September 2014 SN65LVDS822

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（继续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 Power Supply Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Patterns
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Unused LVDS Data Lanes
      2. 9.3.2 Tying CMOS Inputs With Resistors
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active Modes
        1. 9.4.1.1 4-Lanes 7-Bit Mode
        2. 9.4.1.2 2-Lanes 14-Bit Mode
      2. 9.4.2 Low-Power Modes
        1. 9.4.2.1 Standby Mode
        2. 9.4.2.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Color Bit Mapping
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Supply
        2. 10.2.2.2 CMOS Output Bus Connector
        3. 10.2.2.3 Power-Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 商标
    2. 13.2 静电放电警告
    3. 13.3 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

12 Layout

12.1 Layout Guidelines

Use 45 degree bends (chamfered corners), instead of right-angle (90°) bends. Right-angle bends increase the effective trace width, which changes the differential trace impedance creating large discontinuities. A 45o bends is seen as a smaller discontinuity.

Place passive components within the signal path, such as source-matching resistors or ac-coupling capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b), the resulting discontinuity, however, is limited to a far narrower area.

When routing traces next to a via or between an array of vias, make sure that the via clearance section does not interrupt the path of the return current on the ground plane below.

Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better impedance matching. Otherwise they will cause the differential impedance to drop below 75 Ω and fail the board during TDR testing.

Use solid power and ground planes for 100 Ω impedance control and minimum power noise.

For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace spacing possible, which is usually specified by the PCB vendor.

Keep the trace length as short as possible to minimize attenuation.

Place bulk capacitors (i.e. 10 μF) close to power sources, such as voltage regulators or where the power is supplied to the PCB.

12.2 Layout Example

layoutex_sllsee8.gifFigure 22. Layout Example
footprintex_sllsee8.gifFigure 23. Footprint Example