ZHCSBQ4B September   2013  – September 2014 SN65LVDS822

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（继续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 Power Supply Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Patterns
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Unused LVDS Data Lanes
      2. 9.3.2 Tying CMOS Inputs With Resistors
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active Modes
        1. 9.4.1.1 4-Lanes 7-Bit Mode
        2. 9.4.1.2 2-Lanes 14-Bit Mode
      2. 9.4.2 Low-Power Modes
        1. 9.4.2.1 Standby Mode
        2. 9.4.2.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Color Bit Mapping
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Supply
        2. 10.2.2.2 CMOS Output Bus Connector
        3. 10.2.2.3 Power-Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 商标
    2. 13.2 静电放电警告
    3. 13.3 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Detailed Description

9.1 Overview

The SN65LVDS822 implements five low-voltage differential signal (LVDS) line receivers: 4 data lanes and 1 clock lane. The clock is internally multiplied by 7 or 14 (depending on pin MODE14), and used for sampling LVDS data. The device operates in either 4-lane 7x mode, or 2-lane 14x mode. Each input lane contains a shift register that converts serial data to parallel. 27 total bits per clock period are deserialized and presented on the CMOS output bus, along with a clock that uses either rising- or falling-edge alignment.

9.2 Functional Block Diagram

fbd_llsee8.gif

9.3 Feature Description

9.3.1 Unused LVDS Data Lanes

When MODE14 = Low and fewer than 4 data lanes are used, or when MODE14 = High and only 1 data lane is used, it’s recommended that the unused lanes are biased with a constant differential voltage. This prevents high-frequency noise from toggling the unused receiver, which injects noise into the device. This is not a hard requirement, but it’s standard best-practice, and the amount of noise varies system-to-system.

Two implementations are shown below, depending on whether the internal termination RID is connected. A reasonable choice for R1 and R2 is 5kΩ, which produce a nominal VID of 34 mV and 0.3 mA of static current. Smaller resistors increase VID and noise floor margin, as well as static current.

bias_rid_connected_llsee8.gifFigure 12. Bias When RID is Connected
bias_rid_disconnected_llsee8.gifFigure 13. Bias When RID is Disconnected

9.3.2 Tying CMOS Inputs With Resistors

The IIH/IIL specifications indicate that 2-state CMOS input pins have an internal pull-down that’s a minimum size of 180 kΩ, and 3-state CMOS input pins have an internal pull-up and pull-down that are a minimum size of
100 kΩ.

2state_cmos_input_llsee8.gifFigure 14. 2-State CMOS Input
3state_cmos_input_llsee8.gifFigure 15. 3-State CMOS Input

CMOS inputs may be directly connected to VDD or GND, or tied through a resistor. Using a resistor creates a voltage divider network, so it’s important to use a small enough resistor to satisfy VIH/VIL at the pin, and to have voltage margin for system noise. When using a resistor, 5 kΩ or smaller is recommended. Of course, 3-state inputs may be left unconnected to select their floating pin state.

9.4 Device Functional Modes

9.4.1 Active Modes

9.4.1.1 4-Lanes 7-Bit Mode

data_bit_low_llsee8.gifFigure 16. Data Bits Within the LVDS Stream (MODE14 = Low)

9.4.1.2 2-Lanes 14-Bit Mode

data_bit_high_llsee8.gifFigure 17. Data Bits Within the LVDS Stream (MODE14 = High)

9.4.2 Low-Power Modes

9.4.2.1 Standby Mode

In order to decrease the power consumption, the SN65LVDS822 automatically enters to standby when the LVDS clock is inactive.

9.4.2.2 Shutdown Mode

This is the lower-power mode, and the SN65LVDS822 enters to this mode only when the SHTDN# terminal is tied to low.

NOTE

In both low-power modes, all CMOS outputs drive low. All input pins have failsafe protection that prevents damage from occurring before power supply voltages are high and stable.