ZHCSE43 July   2015 SN65HVD63

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Coaxial Interface
      2. 9.3.2 Reference Input
      3. 9.3.3 RS-485 Direction Control
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driver Amplitude Adjust
      2. 10.1.2 Direction Control
      3. 10.1.3 Direction Control Time Constant
      4. 10.1.4 Conversion Between dBm and Peak-to-Peak Voltage
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关文档　
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage, VCC and VL –0.5 6 V
Voltage at coax pins –0.5 6 V
Voltage at logic pins –0.3 VVL + 0.3 V
Logic output current –20 20 mA
TXOUT output current Internally limited
SYNCOUT output current Internally limited
Junction temperature, TJ 170 °C
Continuous total power dissipation See the Thermal Information °C
Storage temperature, Tstg(2) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Applicable before the device is installed in the final product.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Analog supply voltage 3 5.5 V
VL Logic supply voltage 1.6 5.5 V
VI(pp) Input signal amplitude at RXIN 1.12 Vpp
VIH High-level input voltage TXIN, DIRSET1, DIRSET2 70%VL VL V
XTAL1, XTAL2 70%VCC VCC
VIL Low-level input voltage TXIN, DIRSET1, DIRSET2 0 30%VL V
XTAL1, XTAL2 0 30%VCC
1/tUI Data signaling rate 9.6 115 kbps
FOSC Oscillator frequency –30 ppm 8.704 30 ppm MHz
ZLOAD Load impedance between TXOUT to RXIN 50 Ω
Load impedance between RXIN and GND at fC (channel) 50 Ω
R1 Bias resistor between BIAS and RES 4.1 kΩ
R2 Bias resistor between RES and GND 10 kΩ
RSYNC Pullup resistor between SYNCOUT and VCC 1 kΩ
VRES Voltage at RES pin 0.7 1.5 V
CC Coupling capacitance between RXIN and coax (channel) 220 nF
CBIAS Capacitance between BIAS and GND 1 µF
TA Operating free-air temperature –40 105 °C
TJ Junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) VQFN UNIT
RGT16 Pins
RθJA Junction-to-ambient thermal resistance 49.4 °C/W
RθJCtop Junction-to-case (top) thermal resistance 64.2 °C/W
RθJB Junction-to-board thermal resistance 22.9 °C/W
ψJT Junction-to-top characterization parameter 1.7 °C/W
ψJB Junction-to-board characterization parameter 22.9 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 25 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
ICC Supply current DIRSET1 = L
DIRSET2 = H		 TXIN = L (active) 28 33 mA
TXIN = H (quiescent) 25 31
TXIN = 115 kbps,
50% duty cycle		 27 33
DIRSET1 = H, DIRSET2 = H (standby) 12 17
IVL Logic supply current TXIN = H, RXIN = DC input 50 µA
PSRR Receiver power supply rejection ratio VTXIN = VL 45 60 dB
LOGIC PINS
VOH High-level logic output voltage
(RXOUT, DIR)		 IOH = –4 mA for VL > 2.4 V,
IOH = –2 mA for VL < 2.4 V		 90%VVL V
VOL Low-level logic output voltage
(RXOUT, DIR)		 IOL = 4 mA for VL > 2.4 V,
IOL = 2 mA for VL < 2.4 V		 10%VVL V
COAX DRIVER
VO(PP) Peak-to-peak output voltage at device pin TXOUT (see Figure 19) VRES = 1.5 V (Maximum setting) 2.24 2.5 VPP
VRES = 0.7 V (Minimum setting) 1.17 1.3
VO(PP) Peak-to-peak voltage at coax out
(see Figure 19)		 VRES = 1.5 V 5 6 dBm
VRES = 0.7 V –0.6 0.3
VO(OFF) Off-state output voltage At TXOUT 1 mVpp
At coax out –60 dBm
Output emissions Coupled to coaxial cable with characteristic impedance of 50 Ω, as shown in Figure 1(1)(2) N/A
fO Output frequency 2.176 MHz
∆f Output frequency variation –100 100 ppm
ZO Output impedance At 100 kHz 0.03 Ω
At 10 MHz 3.5
| IOS | Short-circuit output current TXOUT is also protected by a thermal shutdown circuit during short-circuit faults 300 450 mA
COAX RECEIVER
VIT Input threshold fIN = 2.176 MHz 79 112 158 mVPP
–18 –15 –12 dBm
ZIN Input impedance f = fO 11 21 kΩ
RECEIVER FILTER
fPB Passband VRXIN = 1.12VP_P 1.1 4.17 MHz
fREJ Receiver rejection range 2.176-MHz carrier amplitude of 112.4 mVPP, frequency band of spurious components with 800 mVPP allowed. 1.1 4.17 MHz
tnoise filter Receiver noise filter time (slow bit rate) DIRSET for 9.6 kbps 4 µs
Receiver noise filter time (fast bit rate) DIRSET for > 9.6 kbps 2 µs
XTAL AND SYNC
II Input leakage current XTAL1, XTAL2, 0V < VIN < VCC –15 15 µA
VOL Output low voltage SYNCOUT, with 1-kΩ resistor from SYNCOUT to VCC 0.4 V
(1) Specified by design with a recommended 470-pF capacitor between RXIN and GND. Measurements above 150 MHz are determined by setup.
(2) Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see Figure 21.

7.6 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpAQ, tpQA Coax driver propagation delay See Figure 19 5 µs
tr, tf Coax receiver output rise/fall time CL = 15 pF, RL = 1 kΩ; see Figure 19 20 ns
tPHL, tPLH Receiver propagation delay See Figure 20 5.5 11 µs
Coax receiver output duty cycle VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle 40% 60%
VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle 40% 60%
tDIR Direction control active duration DIRSET2 = GND or OPEN, DIRSET1 = GND or OPEN 1667 µs
DIRSET2 = GND, DIRSET1 = VL 417
DIRSET2 = VL, DIRSET1 = VL 137
tDIRSKEW Direction control skew
(DIR to RXOUT)		 270 ns
tdis Standby disable delay 300 mVPP at 2.176 MHz on RXIN 2 ms
ten Standby enable delay 300 mVPP at 2.176 MHz on RXIN 2 ms

7.7 Typical Characteristics

SN65HVD63 D002_SLLSEO3.gif
50% Duty Cycle CF = 470 pF
Figure 1. Low-Frequency Emissions Spectrum
With 9.6-kbps Signaling Rate
SN65HVD63 D004_SLLSEO3.gif
50% Duty Cycle CF = 470 pF
Figure 3. Low-Frequency Emissions Spectrum
With 38.4-kbps Signaling Rate
SN65HVD63 D006_SLLSEO3.gif
50% Duty Cycle CF = 470 pF
Figure 5. Low-Frequency Emissions Spectrum
With 115.2-kbps Signaling Rate
SN65HVD63 D008_SLLSEO3.gif
Figure 7. Transmitter Output Impedance
SN65HVD63 D010_SLLSEO3.gif
TXIN = VL
Figure 9. Supply Current vs Supply Voltage
While Transmitting
SN65HVD63 D012_SLLSEO3.gif
Figure 11. Supply Current vs Temperature
in Standby Mode
SN65HVD63 D014_SLLSEO3.gif
Figure 13. Transmitter Output Power vs Temperature
SN65HVD63 D016_SLLSEO3.gif
Figure 15. Receiver Input Threshold vs Temperature
SN65HVD63 D018_SLLSEO3.gif
Figure 17. Receiver Duty Cycle
With 9.6 kbps Signaling Rate
SN65HVD63 D003_SLLSEO3.gif
50% Duty Cycle CF = 470 pF
Figure 2. High-Frequency Emissions Spectrum
With 9.6-kbps Signaling Rate
SN65HVD63 D005_SLLSEO3.gif
50% Duty Cycle CF = 470 pF
Figure 4. High-Frequency Emissions Spectrum
With 38.4-kbps Signaling Rate
SN65HVD63 D007_SLLSEO3.gif
50% Duty Cycle CF = 470 pF
Figure 6. High-Frequency Emissions Spectrum
With 115.2-kbps Signaling Rate
SN65HVD63 D009_SLLSEO3.gif
Figure 8. Transmit Power Adjustment
SN65HVD63 D011_SLLSEO3.gif
TXIN = VL
Figure 10. Supply Current vs Supply Voltage
in Standby Mode
SN65HVD63 D013_SLLSEO3.gif
Figure 12. Transmitter Output Power
vs Supply Voltage
SN65HVD63 D015_SLLSEO3.gif
Figure 14. Receiver Input Impedance vs Frequency
SN65HVD63 D017_SLLSEO3.gif
Figure 16. DIR Output Delay vs Temperature
SN65HVD63 D019_SLLSEO3.gif
Figure 18. Receiver Duty Cycle
With 115.2 kbps Signaling Rate