SLVSKC6 December   2025 RES31A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 DC Measurement Configurations
    2. 6.2 AC Measurement Configurations
    3. 6.3 Error Notation and Units
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ratiometric Matching for Low Gain Error
        1. 7.3.1.1 Absolute and Ratiometric Tolerances
      2. 7.3.2 Ratiometric Drift
      3. 7.3.3 Ultra-Low Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Amplifier Feedback Circuit
        1. 8.1.1.1 Amplifier Feedback Circuit Example
      2. 8.1.2 Voltage Divider Circuit
        1. 8.1.2.1 Voltage Divider Circuit Example
        2. 8.1.2.2 Voltage-Divider Circuit Drift
      3. 8.1.3 Discrete Difference Amplifier
        1. 8.1.3.1 Difference-Amplifier Common-Mode Rejection Analysis
        2. 8.1.3.2 Difference-Amplifier Gain Error Analysis
      4. 8.1.4 Discrete Instrumentation Amplifiers
      5. 8.1.5 Fully Differential Amplifier
      6. 8.1.6 Unconventional Circuits
        1. 8.1.6.1 Single-Channel Voltage Divider
        2. 8.1.6.2 Single-Channel Amplifier Gain
        3. 8.1.6.3 Unconventional Instrumentation Amplifiers
    2. 8.2 Typical Application
      1. 8.2.1 Common-Mode Shifting Input Stage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 TI Reference Designs
        4. 9.1.1.4 Analog Filter Designer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

Figure 4-1 DDF Package, 8-Pin SOT-23-THN (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
GND/SUB 4, 8 Ground Substrate bias connection. Only bias one GND/SUB pin. Float the other GND/SUB pin to prevent current return paths from forming through the substrate. See also Section 7.4.
RG1 3 Input Gain resistor connection for divider 1
RG2 5 Input Gain resistor connection for divider 2
RIN1 1 Input Input resistor connection for divider 1
RIN2 7 Input Input resistor connection for divider 2
RMID1 2 Output Center tap of divider 1
RMID2 6 Output Center tap of divider 2