ZHCSMY3 December   2020 PCM6020-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3 Input Channel Configuration
      4. 8.3.4 Reference Voltage
      5. 8.3.5 Microphone Bias
      6. 8.3.6 Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.7.2 Programmable Channel Gain Calibration
        3. 8.3.7.3 Programmable Channel Phase Calibration
        4. 8.3.7.4 Programmable Digital High-Pass Filter
        5. 8.3.7.5 Programmable Digital Biquad Filters
        6. 8.3.7.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.7.7 Configurable Digital Decimation Filters
          1. 8.3.7.7.1 Linear Phase Filters
            1. 8.3.7.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.7.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.7.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.7.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.7.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.7.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.7.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.7.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.7.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.7.7.2 Low-Latency Filters
            1. 8.3.7.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.7.7.3 Ultra-Low-Latency Filters
            1. 8.3.7.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.7.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      8. 8.3.8 Automatic Gain Controller (AGC)
      9. 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Registers Access Type
        2. 8.6.1.2 Page 0 Registers
        3. 8.6.1.3 Page 1 Registers
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page 2
        2. 8.6.2.2 Programmable Coefficient Registers: Page 3
        3. 8.6.2.3 Programmable Coefficient Registers: Page 4
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 2-Channel Analog Microphone Recording Using the PCM6020-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表

封装选项

机械数据 (封装 | 引脚)
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订购信息

Programmable Coefficient Registers: Page 2

This register page (shown in GUID-7EEEFD7F-C861-40EF-882E-C2C5F872FCCD.html#T5453282-93B) consists of the programmable coefficients for the biquad 1 to biquad 6 filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads. After a transaction of register address 0x7F, the device auto increments to the next page at register 0x08 to transact the next coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For a successful coefficient register transaction, the host device must write and read all four bytes starting with the most significant byte (BYT1) for a target coefficient register transaction. When using SPI for a coefficient register read transaction, the device transmits the first byte as a dummy read byte; therefore, the host must read five bytes, including the first dummy read byte and the last four bytes corresponding to the coefficient register value starting with the most significant byte (BYT1).

Table 8-142 Page 2 Programmable Coefficient Registers
ADDRESS ACRONYM RESET VALUE REGISTER DESCRIPTION
0x00 PAGE[7:0] 0x00 GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#GUID-DDC1CAE0-C88B-4636-AB28-57820F74FE0E
0x08 BQ1_N0_BYT1[7:0] 0x7F Programmable biquad 1, N0 coefficient byte[31:24]
0x09 BQ1_N0_BYT2[7:0] 0xFF Programmable biquad 1, N0 coefficient byte[23:16]
0x0A BQ1_N0_BYT3[7:0] 0xFF Programmable biquad 1, N0 coefficient byte[15:8]
0x0B BQ1_N0_BYT4[7:0] 0xFF Programmable biquad 1, N0 coefficient byte[7:0]
0x0C BQ1_N1_BYT1[7:0] 0x00 Programmable biquad 1, N1 coefficient byte[31:24]
0x0D BQ1_N1_BYT2[7:0] 0x00 Programmable biquad 1, N1 coefficient byte[23:16]
0x0E BQ1_N1_BYT3[7:0] 0x00 Programmable biquad 1, N1 coefficient byte[15:8]
0x0F BQ1_N1_BYT4[7:0] 0x00 Programmable biquad 1, N1 coefficient byte[7:0]
0x10 BQ1_N2_BYT1[7:0] 0x00 Programmable biquad 1, N2 coefficient byte[31:24]
0x11 BQ1_N2_BYT2[7:0] 0x00 Programmable biquad 1, N2 coefficient byte[23:16]
0x12 BQ1_N2_BYT3[7:0] 0x00 Programmable biquad 1, N2 coefficient byte[15:8]
0x13 BQ1_N2_BYT4[7:0] 0x00 Programmable biquad 1, N2 coefficient byte[7:0]
0x14 BQ1_D1_BYT1[7:0] 0x00 Programmable biquad 1, D1 coefficient byte[31:24]
0x15 BQ1_D1_BYT2[7:0] 0x00 Programmable biquad 1, D1 coefficient byte[23:16]
0x16 BQ1_D1_BYT3[7:0] 0x00 Programmable biquad 1, D1 coefficient byte[15:8]
0x17 BQ1_D1_BYT4[7:0] 0x00 Programmable biquad 1, D1 coefficient byte[7:0]
0x18 BQ1_D2_BYT1[7:0] 0x00 Programmable biquad 1, D2 coefficient byte[31:24]
0x19 BQ1_D2_BYT2[7:0] 0x00 Programmable biquad 1, D2 coefficient byte[23:16]
0x1A BQ1_D2_BYT3[7:0] 0x00 Programmable biquad 1, D2 coefficient byte[15:8]
0x1B BQ1_D2_BYT4[7:0] 0x00 Programmable biquad 1, D2 coefficient byte[7:0]
0x1C BQ2_N0_BYT1[7:0] 0x7F Programmable biquad 2, N0 coefficient byte[31:24]
0x1D BQ2_N0_BYT2[7:0] 0xFF Programmable biquad 2, N0 coefficient byte[23:16]
0x1E BQ2_N0_BYT3[7:0] 0xFF Programmable biquad 2, N0 coefficient byte[15:8]
0x1F BQ2_N0_BYT4[7:0] 0xFF Programmable biquad 2, N0 coefficient byte[7:0]
0x20 BQ2_N1_BYT1[7:0] 0x00 Programmable biquad 2, N1 coefficient byte[31:24]
0x21 BQ2_N1_BYT2[7:0] 0x00 Programmable biquad 2, N1 coefficient byte[23:16]
0x22 BQ2_N1_BYT3[7:0] 0x00 Programmable biquad 2, N1 coefficient byte[15:8]
0x23 BQ2_N1_BYT4[7:0] 0x00 Programmable biquad 2, N1 coefficient byte[7:0]
0x24 BQ2_N2_BYT1[7:0] 0x00 Programmable biquad 2, N2 coefficient byte[31:24]
0x25 BQ2_N2_BYT2[7:0] 0x00 Programmable biquad 2, N2 coefficient byte[23:16]
0x26 BQ2_N2_BYT3[7:0] 0x00 Programmable biquad 2, N2 coefficient byte[15:8]
0x27 BQ2_N2_BYT4[7:0] 0x00 Programmable biquad 2, N2 coefficient byte[7:0]
0x28 BQ2_D1_BYT1[7:0] 0x00 Programmable biquad 2, D1 coefficient byte[31:24]
0x29 BQ2_D1_BYT2[7:0] 0x00 Programmable biquad 2, D1 coefficient byte[23:16]
0x2A BQ2_D1_BYT3[7:0] 0x00 Programmable biquad 2, D1 coefficient byte[15:8]
0x2B BQ2_D1_BYT4[7:0] 0x00 Programmable biquad 2, D1 coefficient byte[7:0]
0x2C BQ2_D2_BYT1[7:0] 0x00 Programmable biquad 2, D2 coefficient byte[31:24]
0x2D BQ2_D2_BYT2[7:0] 0x00 Programmable biquad 2, D2 coefficient byte[23:16]
0x2E BQ2_D2_BYT3[7:0] 0x00 Programmable biquad 2, D2 coefficient byte[15:8]
0x2F BQ2_D2_BYT4[7:0] 0x00 Programmable biquad 2, D2 coefficient byte[7:0]
0x58 BQ5_N0_BYT1[7:0] 0x7F Programmable biquad 5, N0 coefficient byte[31:24]
0x59 BQ5_N0_BYT2[7:0] 0xFF Programmable biquad 5, N0 coefficient byte[23:16]
0x5A BQ5_N0_BYT3[7:0] 0xFF Programmable biquad 5, N0 coefficient byte[15:8]
0x5B BQ5_N0_BYT4[7:0] 0xFF Programmable biquad 5, N0 coefficient byte[7:0]
0x5C BQ5_N1_BYT1[7:0] 0x00 Programmable biquad 5, N1 coefficient byte[31:24]
0x5D BQ5_N1_BYT2[7:0] 0x00 Programmable biquad 5, N1 coefficient byte[23:16]
0x5E BQ5_N1_BYT3[7:0] 0x00 Programmable biquad 5, N1 coefficient byte[15:8]
0x5F BQ5_N1_BYT4[7:0] 0x00 Programmable biquad 5, N1 coefficient byte[7:0]
0x60 BQ5_N2_BYT1[7:0] 0x00 Programmable biquad 5, N2 coefficient byte[31:24]
0x61 BQ5_N2_BYT2[7:0] 0x00 Programmable biquad 5, N2 coefficient byte[23:16]
0x62 BQ5_N2_BYT3[7:0] 0x00 Programmable biquad 5, N2 coefficient byte[15:8]
0x63 BQ5_N2_BYT4[7:0] 0x00 Programmable biquad 5, N2 coefficient byte[7:0]
0x64 BQ5_D1_BYT1[7:0] 0x00 Programmable biquad 5, D1 coefficient byte[31:24]
0x65 BQ5_D1_BYT2[7:0] 0x00 Programmable biquad 5, D1 coefficient byte[23:16]
0x66 BQ5_D1_BYT3[7:0] 0x00 Programmable biquad 5, D1 coefficient byte[15:8]
0x67 BQ5_D1_BYT4[7:0] 0x00 Programmable biquad 5, D1 coefficient byte[7:0]
0x68 BQ5_D2_BYT1[7:0] 0x00 Programmable biquad 5, D2 coefficient byte[31:24]
0x69 BQ5_D2_BYT2[7:0] 0x00 Programmable biquad 5, D2 coefficient byte[23:16]
0x6A BQ5_D2_BYT3[7:0] 0x00 Programmable biquad 5, D2 coefficient byte[15:8]
0x6B BQ5_D2_BYT4[7:0] 0x00 Programmable biquad 5, D2 coefficient byte[7:0]
0x6C BQ6_N0_BYT1[7:0] 0x7F Programmable biquad 6, N0 coefficient byte[31:24]
0x6D BQ6_N0_BYT2[7:0] 0xFF Programmable biquad 6, N0 coefficient byte[23:16]
0x6E BQ6_N0_BYT3[7:0] 0xFF Programmable biquad 6, N0 coefficient byte[15:8]
0x6F BQ6_N0_BYT4[7:0] 0xFF Programmable biquad 6, N0 coefficient byte[7:0]
0x70 BQ6_N1_BYT1[7:0] 0x00 Programmable biquad 6, N1 coefficient byte[31:24]
0x71 BQ6_N1_BYT2[7:0] 0x00 Programmable biquad 6, N1 coefficient byte[23:16]
0x72 BQ6_N1_BYT3[7:0] 0x00 Programmable biquad 6, N1 coefficient byte[15:8]
0x73 BQ6_N1_BYT4[7:0] 0x00 Programmable biquad 6, N1 coefficient byte[7:0]
0x74 BQ6_N2_BYT1[7:0] 0x00 Programmable biquad 6, N2 coefficient byte[31:24]
0x75 BQ6_N2_BYT2[7:0] 0x00 Programmable biquad 6, N2 coefficient byte[23:16]
0x76 BQ6_N2_BYT3[7:0] 0x00 Programmable biquad 6, N2 coefficient byte[15:8]
0x77 BQ6_N2_BYT4[7:0] 0x00 Programmable biquad 6, N2 coefficient byte[7:0]
0x78 BQ6_D1_BYT1[7:0] 0x00 Programmable biquad 6, D1 coefficient byte[31:24]
0x79 BQ6_D1_BYT2[7:0] 0x00 Programmable biquad 6, D1 coefficient byte[23:16]
0x7A BQ6_D1_BYT3[7:0] 0x00 Programmable biquad 6, D1 coefficient byte[15:8]
0x7B BQ6_D1_BYT4[7:0] 0x00 Programmable biquad 6, D1 coefficient byte[7:0]
0x7C BQ6_D2_BYT1[7:0] 0x00 Programmable biquad 6, D2 coefficient byte[31:24]
0x7D BQ6_D2_BYT2[7:0] 0x00 Programmable biquad 6, D2 coefficient byte[23:16]
0x7E BQ6_D2_BYT3[7:0] 0x00 Programmable biquad 6, D2 coefficient byte[15:8]
0x7F BQ6_D2_BYT4[7:0] 0x00 Programmable biquad 6, D2 coefficient byte[7:0]