ZHCSL25 April   2019 PCM1840

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
        3. 7.3.2.3 Left-Justified (LJ) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Input Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 Digital High-Pass Filter
        2. 7.3.7.2 Configurable Digital Decimation Filters
          1. 7.3.7.2.1 Linear Phase Filters
            1. 7.3.7.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 7.3.7.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 7.3.7.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 7.3.7.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 7.3.7.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 7.3.7.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 7.3.7.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 7.3.7.2.2 Low-Latency Filters
            1. 7.3.7.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.7.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.7.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.7.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.7.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 7.3.8 Dynamic Range Enhancer (DRE)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Shutdown
      2. 7.4.2 Active Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.2.1 Time Division Multiplexed Audio (TDM) Interface

In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK. Figure 14 to Figure 17 illustrate the protocol timing for TDM operation with various configurations.

PCM1840 tdm-01-pcm1840-sbas989.gifFigure 14. TDM Mode Protocol Timing (FMT0 = LOW) In Slave Mode
PCM1840 tdm-02-pcm1840-sbas989.gifFigure 15. TDM Mode Protocol Timing (FMT0 = HIGH) In Slave Mode
PCM1840 tdm-03-pcm1840-sbas989.gifFigure 16. TDM Mode Protocol Timing (FMT0 = LOW) In Master Mode
PCM1840 tdm-04-pcm1840-sbas989.gifFigure 17. TDM Mode Protocol Timing (FMT0 = HIGH) In Master Mode

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels times the 32-bits word length of the output channel data. The device transmits a zero data value on SDOUT for the extra unused bit clock cycles. The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well.