ZHCSL25 April   2019 PCM1840

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     简化方框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
        3. 7.3.2.3 Left-Justified (LJ) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Input Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 Digital High-Pass Filter
        2. 7.3.7.2 Configurable Digital Decimation Filters
          1. 7.3.7.2.1 Linear Phase Filters
            1. 7.3.7.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 7.3.7.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 7.3.7.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 7.3.7.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 7.3.7.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 7.3.7.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 7.3.7.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 7.3.7.2.2 Low-Latency Filters
            1. 7.3.7.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.7.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.7.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.7.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.7.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 7.3.8 Dynamic Range Enhancer (DRE)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Shutdown
      2. 7.4.2 Active Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Overview

The PCM1840 is a high-performance, low-power, quad-channel, audio analog-to-digital converter (ADC) with flexible audio interface control options. This device is intended for applications in voice-activated systems, AV receivers, TV and blu-ray players, professional microphones, audio conferencing, portable computing, communication, and entertainment applications. The high dynamic range of the device enables far-field audio recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power consumption in space-constrained, battery-powered, consumer, home, and industrial applications. The device features are controlled through hardware by pulling pins high or low with resistors or a controller GPIO. The PCM1808 also supports a power-down and reset function by means of halting the system clock.

The PCM1840 consists of the following blocks and features:

  • Quad-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
  • Differential audio inputs with a 2-VRMS full-scale signal
  • Low-noise, 1.6-µVRMS, microphone bias output
  • Hardware pin control operation to select the device features
  • Audio bus serial interface master or slave select option
  • Audio bus serial interface format select option
  • Audio bus serial interface supported up to 192 kHz sampling
  • Slave mode supports dynamic range enhancer (DRE) with 123-dB dynamic range
  • Slave mode supports decimation filters with linear-phase or low-latency filter selection
  • Master mode operation supported using system clock of 256 × fS or 512 × fS
  • Power-down function by means of halting the audio clocks
  • Integrated high-pass filter (HPF) that removes the dc component of the input signal
  • Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
  • Integrated digital and analog voltage regulators to support single-supply 3.3-V operation