ZHCSDF2E October   2014  – December 2019 MSP430FR2032 , MSP430FR2033

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2 Reset Timing
        1. Table 5-2 Wake-Up Times From Low-Power Modes and Reset
      3. 5.12.3 Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 REFO
        4. Table 5-6 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-7 Module Oscillator Clock (MODCLK)
      4. 5.12.4 Digital I/Os
        1. Table 5-8 Digital Inputs
        2. Table 5-9 Digital Outputs
        3. 5.12.4.1  Digital I/O Typical Characteristics
      5. 5.12.5 Timer_A
        1. Table 5-10 Timer_A Recommended Operating Conditions
      6. 5.12.6 eUSCI
        1. Table 5-11 eUSCI (UART Mode) Recommended Operating Conditions
        2. Table 5-12 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-13 eUSCI (SPI Master Mode) Recommended Operating Conditions
        4. Table 5-14 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-15 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-16 eUSCI (I2C Mode) Switching Characteristics
      7. 5.12.7 ADC
        1. Table 5-17 ADC, Power Supply and Input Range Conditions
        2. Table 5-18 ADC, 10-Bit Timing Parameters
        3. Table 5-19 ADC, 10-Bit Linearity Parameters
      8. 5.12.8 FRAM
        1. Table 5-20 FRAM
      9. 5.12.9 Emulation and Debug
        1. Table 5-21 JTAG and Spy-Bi-Wire Interface Characteristics
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Bootloader (BSL)
    5. 6.5  JTAG Standard Interface
    6. 6.6  Spy-Bi-Wire Interface (SBW)
    7. 6.7  FRAM
    8. 6.8  Memory Protection
    9. 6.9  Peripherals
      1. 6.9.1  Power Management Module (PMM) and On-chip Reference Voltages
      2. 6.9.2  Clock System (CS) and Clock Distribution
      3. 6.9.3  General-Purpose Input/Output Port (I/O)
      4. 6.9.4  Watchdog Timer (WDT)
      5. 6.9.5  System Module (SYS)
      6. 6.9.6  Cyclic Redundancy Check (CRC)
      7. 6.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.9.9  Real-Time Clock (RTC) Counter
      10. 6.9.10 10-Bit Analog Digital Converter (ADC)
      11. 6.9.11 Embedded Emulation Module (EEM)
      12. 6.9.12 Input/Output Diagrams
        1. 6.9.12.1  Port P1 Input/Output With Schmitt Trigger
        2. 6.9.12.2  Port P2 Input/Output With Schmitt Trigger
        3. 6.9.12.3  Port P3 Input/Output With Schmitt Trigger
        4. 6.9.12.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 6.9.12.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 6.9.12.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 6.9.12.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 6.9.12.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 6.9.12.9  Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
        10. 6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
        11. 6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
        12. 6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
        13. 6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        14. 6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 6.10 Device Descriptors (TLV)
    11. 6.11 Memory
      1. 6.11.1 Peripheral File Map
    12. 6.12 Identification
      1. 6.12.1 Revision Identification
      2. 6.12.2 Device Identification
      3. 6.12.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 开始使用
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 社区资源
    7. 8.7 商标
    8. 8.8 静电放电警告
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

2 修订历史记录

从修订版本 D 更改为修订版本 E

Changes from January 22, 2019 to December 9, 2019

  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating ConditionsGo
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Added the t(int) parameter in Table 5-8, Digital InputsGo
  • Corrected the test conditions for the RI,MUX parameter in Table 5-17, ADC, Power Supply and Input Range ConditionsGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-18, ADC, 10-Bit Timing ParametersGo

Changes from August 30, 2018 to January 21, 2019

  • 已通篇将调制振荡器 (MODOSC) 更改为调制振荡器时钟 (MODCLK)Go
  • Added "or memory corruption" to note (1) in Section 5.1, Absolute Maximum RatingsGo
  • Added the note that begins "The VLO clock frequency is reduced by..." after Table 5-6, Internal Very-Low-Power Low-Frequency Oscillator (VLO)Go
  • Changed the parameter symbol from RI to RI,MUX in Table 5-17, ADC, Power Supply and Input Range ConditionsGo
  • Added the RI,Misc parameter in Table 5-17, ADC, Power Supply and Input Range ConditionsGo
  • Removed ADCDIV from the formula for the tCONVERT TYP value, because ADCCLK is after division, in Table 5-18, ADC, 10-Bit Timing ParametersGo
  • Added note (2) for RI calculation in Table 5-18, ADC, 10-Bit Timing ParametersGo
  • Removed "±3°C" on both temperatures in the note that begins "The device descriptor structure contains..." in Table 5-19, ADC, 10-Bit Linearity Parameters Go
  • Add "10b" for ADCSSEL bit in Table 6-6, Clock DistributionGo
  • Added Figure 6-1, Clock Distribution Block DiagramGo
  • Corrected the spelling of the IRDSSEL bit in the paragraph that begins "The IR functions are controlled by..." in Section 6.9.8, Timers (Timer0_A3, Timer1_A3)Go
  • Changed two instances of "ADC 1.5-V Reference Temperature" to "ADC 1.5-V Reference Temperature Sensor" in Table 6-29, Device DescriptorsGo

Changes from August 15, 2015 to August 29, 2018

  • Updated Section 3.1, Related ProductsGo
  • Replaced all notes on Section 5.11, Thermal CharacteristicsGo
  • Added note to VSVSH- and VSVSH+ parameters in Table 5-1, PMM, SVS and BORGo
  • Updated the link to the BSL user's guide in Section 6.4, Bootloader (BSL)Go
  • Changed all instances of "bootstrap loader" to "bootloader" throughout documentGo
  • Corrected the ADCINCHx column heading in Table 6-12, ADC Channel ConnectionsGo
  • 更新了Section 8，器件和文档支持 中的特定于器件的信息和链接Go

Changes from December 23, 2014 to August 14, 2015

  • Corrected "10-BIT ADC CHANNELS" column for MSP430FR2032IPM in Table 3-1, Device ComparisonGo
  • Added Tstg MIN and MAX valuesGo
  • Added Section 5.2, ESD RatingsGo
  • Changed all graphs in Section 5.9, Typical Characteristics, Low-Power Mode Supply Currents, for new measurements Go
  • Added VREF, 1.2V parameter to Table 5-1, PMM, SVS and BORGo
  • Changed tSTE,LEAD MIN value at 2 V from 40 ns to 50 nsGo
  • Changed tSTE,LEAD MIN value at 3 V from 24 ns to 45 nsGo
  • Changed tVALID,SO MAX value at 2 V from 55 ns to 65 nsGo
  • Changed tVALID,SO MAX value at 3 V from 30 ns to 40 nsGo
  • Changed the fADCOSC TYP value from 4.5 MHz to 5.0 MHzGo
  • In Table 6-1, Operating Modes, changed the entry for "Power Consumption at 25°C, 3 V" in AM from 100 µA/MHz to 126 µA/MHzGo
  • In Table 6-1, Operating Modes, added "with RTC only" to the entry for "Power Consumption at 25°C, 3 V" in LPM3.5Go
  • In Table 6-2, Interrupt Sources, Flags, and Vectors, removed "FRAM access time error" (ACCTEIFG) from the "System NMI" row Go

Changes from October 3, 2014 to December 22, 2014

  • Moved Tstg to Absolute Maximum RatingsGo
  • Changed link to BSL user's guide in Section 6.4, Bootloader (BSL)Go
  • Added note (1) to Table 6-6Go
  • Changed the values of ADC Calibration Tag and ADC Calibration Length in the ADC Calibration rowGo
  • Added Calibration Tag, Calibration Length, and 1.5-V Reference in the Reference and DCO Calibration rowGo
  • Added row for BSL memory to Table 6-30Go