ZHCSA42F August   2010  – September 2020 MSP430F5333 , MSP430F5335 , MSP430F5336 , MSP430F5338

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 8.8  Inputs – Ports P1, P2, P3, and P4
    9. 8.9  Leakage Current – General-Purpose I/O
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 8.12 Output Frequency – Ports P1, P2, and P3
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT2
    17. 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 8.19 DCO Frequency
    20. 8.20 PMM, Brownout Reset (BOR)
    21. 8.21 PMM, Core Voltage
    22. 8.22 PMM, SVS High Side
    23. 8.23 PMM, SVM High Side
    24. 8.24 PMM, SVS Low Side
    25. 8.25 PMM, SVM Low Side
    26. 8.26 Wake-up Times From Low-Power Modes and Reset
    27. 8.27 Timer_A, Timers TA0, TA1, and TA2
    28. 8.28 Timer_B, Timer TB0
    29. 8.29 Battery Backup
    30. 8.30 USCI (UART Mode)
    31. 8.31 USCI (SPI Master Mode)
    32. 8.32 USCI (SPI Slave Mode)
    33. 8.33 USCI (I2C Mode)
    34. 8.34 12-Bit ADC, Power Supply and Input Range Conditions
    35. 8.35 12-Bit ADC, Timing Parameters
    36. 8.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    37. 8.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    38. 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 8.40 REF, External Reference
    41. 8.41 REF, Built-In Reference
    42. 8.42 12-Bit DAC, Supply Specifications
    43. 8.43 12-Bit DAC, Linearity Specifications
    44. 8.44 12-Bit DAC, Output Specifications
    45. 8.45 12-Bit DAC, Reference Input Specifications
    46. 8.46 12-Bit DAC, Dynamic Specifications
    47. 8.47 12-Bit DAC, Dynamic Specifications (Continued)
    48. 8.48 Comparator_B
    49. 8.49 Ports PU.0 and PU.1
    50. 8.50 LDO-PWR (LDO Power System)
    51. 8.51 Flash Memory
    52. 8.52 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  Memory
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power-Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 ADC12_A
      17. 9.12.17 DAC12_A
      18. 9.12.18 CRC16
      19. 9.12.19 Voltage Reference (REF) Module
      20. 9.12.20 LDO and PU Port
      21. 9.12.21 Embedded Emulation Module (EEM)
      22. 9.12.22 Peripheral File Map
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 9.13.13 Port PU (PU.0 and PU.1) Ports
      14. 9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  支持资源
    7. 10.7  Trademarks
    8. 10.8  静电放电警告
    9. 10.9  Export Control Notice
    10. 10.10 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.2 Signal Descriptions

Table 7-1 describes the signals for all device variants and packages.

Table 7-1 Signal Descriptions
TERMINAL I/O(1) DESCRIPTION
NAME NO.(4)
PZ ZCA, ZQW
P6.4/CB4/A4 1 A1 I/O General-purpose digital I/O

Comparator_B input CB4

Analog input A4 – ADC

P6.5/CB5/A5 2 B2 I/O General-purpose digital I/O

Comparator_B input CB5

Analog input A5 – ADC

P6.6/CB6/A6/DAC0 3 B1 I/O General-purpose digital I/O

Comparator_B input CB6

Analog input A6 – ADC

DAC12.0 output (not available on F5335 and F5333 devices)
P6.7/CB7/A7/DAC1 4 C2 I/O General-purpose digital I/O

Comparator_B input CB7

Analog input A7 – ADC

DAC12.1 output (not available on F5335 and F5333 devices)
P7.4/CB8/A12 5 C1 I/O General-purpose digital I/O

Comparator_B input CB8

Analog input A12 –ADC

P7.5/CB9/A13 6 C3 I/O General-purpose digital I/O

Comparator_B input CB9

Analog input A13 – ADC

P7.6/CB10/A14/DAC0 7 D2 I/O General-purpose digital I/O

Comparator_B input CB10

Analog input A14 – ADC

DAC12.0 output (not available on F5335 and F5333 devices)
P7.7/CB11/A15/DAC1 8 D1 I/O General-purpose digital I/O

Comparator_B input CB11

Analog input A15 – ADC

DAC12.1 output (not available on F5335 and F5333 devices)
P5.0/VREF+/VeREF+ 9 D4 I/O General-purpose digital I/O

Output of reference voltage to the ADC

Input for an external reference voltage to the ADC
P5.1/VREF-/VeREF- 10 E4 I/O General-purpose digital I/O

Negative terminal for the reference voltage of the ADC for both sources, the internal reference voltage, or an external applied reference voltage
AVCC1 11 E1, E2 Analog power supply
AVSS1 12 F2 Analog ground supply
XIN 13 F1 I Input terminal for crystal oscillator XT1
XOUT 14 G1 O Output terminal of crystal oscillator XT1
AVSS2 15 G2 Analog ground supply
P5.6/ADC12CLK/DMAE0 16 H1 I/O General-purpose digital I/O

Conversion clock output ADC

DMA external trigger input
P2.0/P2MAP0 17 G4 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
P2.1/P2MAP1 18 H2 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
P2.2/P2MAP2 19 J1 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
P2.3/P2MAP3 20 H4 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
P2.4/P2MAP4 21 J2 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
P2.5/P2MAP5 22 K1 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
P2.6/P2MAP6 23 K2 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function
P2.7/P2MAP7 24 L2 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function
DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply
VCORE(2) 27 M2 Regulated core power supply (internal use only, no external current loading)
P5.2 28 L3 I/O General-purpose digital I/O
DVSS 29 M3 Digital ground supply
DNC 30 J4 Do not connect. It is strongly recommended to leave this terminal open.
P5.3 31 L4 I/O General-purpose digital I/O
P5.4 32 M4 I/O General-purpose digital I/O
P5.5 33 J5 I/O General-purpose digital I/O
P1.0/TA0CLK/ACLK 34 L5 I/O General-purpose digital I/O with port interrupt

Timer TA0 clock signal TACLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 35 M5 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output
P1.2/TA0.1 36 J6 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input
P1.3/TA0.2 37 H6 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 38 M6 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 39 L6 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA0.1 40 J7 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
P1.7/TA0.2 41 M7 I/O General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
P3.0/TA1CLK/CBOUT 42 L7 I/O General-purpose digital I/O with port interrupt

Timer TA1 clock input

Comparator_B output
P3.1/TA1.0 43 H7 I/O General-purpose digital I/O with port interrupt

Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
P3.2/TA1.1 44 M8 I/O General-purpose digital I/O with port interrupt

Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
P3.3/TA1.2 45 L8 I/O General-purpose digital I/O with port interrupt

Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
P3.4/TA2CLK/SMCLK 46 J8 I/O General-purpose digital I/O with port interrupt

Timer TA2 clock input

SMCLK output
P3.5/TA2.0 47 M9 I/O General-purpose digital I/O with port interrupt

Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
P3.6/TA2.1 48 L9 I/O General-purpose digital I/O with port interrupt

Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
P3.7/TA2.2 49 M10 I/O General-purpose digital I/O with port interrupt

Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
P4.0/TB0.0 50 J9 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
P4.1/TB0.1 51 M11 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
P4.2/TB0.2 52 L10 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
P4.3/TB0.3 53 M12 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
P4.4/TB0.4 54 L12 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
P4.5/TB0.5 55 L11 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
P4.6/TB0.6 56 K11 I/O General-purpose digital I/O with port interrupt

Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
P4.7/TB0OUTH/SVMOUT 57 K12 I/O General-purpose digital I/O with port interrupt

Timer TB0: Switch all PWM outputs high impedance

SVM output
P8.0/TB0CLK 58 J11 I/O General-purpose digital I/O

Timer TB0 clock input
P8.1/UCB1STE/UCA1CLK 59 J12 I/O General-purpose digital I/O

USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output
P8.2/UCA1TXD/UCA1SIMO 60 H11 I/O General-purpose digital I/O

USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out
P8.3/UCA1RXD/UCA1SOMI 61 H12 I/O

General-purpose digital I/O

USCI_A1 UART receive data; USCI_A1 SPI slave out/master in
P8.4/UCB1CLK/UCA1STE 62 G11 I/O General-purpose digital I/O

USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable
DVSS2 63 G12 Digital ground supply
DVCC2 64 F12 Digital power supply
P8.5/UCB1SIMO/UCB1SDA 65 F11 I/O General-purpose digital I/O

USCI_B1 SPI slave in/master out; USCI_B1 I2C data

P8.6/UCB1SOMI/UCB1SCL 66 G9 I/O General-purpose digital I/O

USCI_B1 SPI slave out/master in; USCI_B1 I2C clock
P8.7 67 E12 I/O General-purpose digital I/O
P9.0 68 E11 I/O General-purpose digital I/O
P9.1 69 F9 I/O General-purpose digital I/O
P9.2 70 D12 I/O General-purpose digital I/O
P9.3 71 D11 I/O

General-purpose digital I/O

P9.4 72 E9 I/O General-purpose digital I/O
P9.5 73 C12 I/O General-purpose digital I/O
P9.6 74 C11 I/O General-purpose digital I/O
P9.7 75 D9 I/O General-purpose digital I/O
VSSU 76 B11, B12 PU ground supply
PU.0 77 A12 I/O General-purpose digital I/O, controlled by PU control register. Port U is supplied by the LDOO rail.
NC 78 B10 No connect
PU.1 79 A11 I/O General-purpose digital I/O, controlled by PU control register. Port U is supplied by the LDOO rail.
LDOI 80 A10 LDO input
LDOO 81 A9 LDO output
NC 82 B9 No connect
AVSS3 83 A8 Analog ground supply
P7.2/XT2IN 84 B8 I/O General-purpose digital I/O

Input terminal for crystal oscillator XT2
P7.3/XT2OUT 85 B7 I/O General-purpose digital I/O

Output terminal of crystal oscillator XT2
VBAK 86 A7 Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Section 8.3.
VBAT 87 D8 Backup or secondary supply voltage. If backup voltage is not supplied, connect to DVCC externally.
P5.7/RTCCLK 88 D7 I/O General-purpose digital I/O

RTCCLK output
DVCC3 89 A6 Digital power supply
DVSS3 90 A5 Digital ground supply
TEST/SBWTCK 91 B6 I Test mode pin; selects digital I/O on JTAG pins

Spy-Bi-Wire input clock
PJ.0/TDO 92 B5 I/O General-purpose digital I/O

Test data output port
PJ.1/TDI/TCLK 93 A4 I/O General-purpose digital I/O

Test data input or test clock input
PJ.2/TMS 94 E7 I/O General-purpose digital I/O

Test mode select
PJ.3/TCK 95 D6 I/O General-purpose digital I/O

Test clock
RST/NMI/SBWTDIO 96 A3 I/O Reset input (active low)(3)

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
P6.0/CB0/A0 97 B4 I/O General-purpose digital I/O

Comparator_B input CB0

Analog input A0 – ADC

P6.1/CB1/A1 98 B3 I/O General-purpose digital I/O

Comparator_B input CB1

Analog input A1 – ADC

P6.2/CB2/A2 99 A2 I/O General-purpose digital I/O

Comparator_B input CB2

Analog input A2 – ADC

P6.3/CB3/A3 100 D5 I/O General-purpose digital I/O

Comparator_B input CB3

Analog input A3 – ADC

Reserved N/A E5, E6, E8, F4, F5, F8, G5, G8, H5, H8, H9 Reserved. TI recommends connecting to ground (DVSS, AVSS).
(1) I = input, O = output, N/A = not available on this package offering
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(4) See the Package Option Addendum in Section 11 to determine which devices are available in each package.