ZHCSA42F August   2010  – September 2020 MSP430F5333 , MSP430F5335 , MSP430F5336 , MSP430F5338

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 8.8  Inputs – Ports P1, P2, P3, and P4
    9. 8.9  Leakage Current – General-Purpose I/O
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 8.12 Output Frequency – Ports P1, P2, and P3
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT2
    17. 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 8.19 DCO Frequency
    20. 8.20 PMM, Brownout Reset (BOR)
    21. 8.21 PMM, Core Voltage
    22. 8.22 PMM, SVS High Side
    23. 8.23 PMM, SVM High Side
    24. 8.24 PMM, SVS Low Side
    25. 8.25 PMM, SVM Low Side
    26. 8.26 Wake-up Times From Low-Power Modes and Reset
    27. 8.27 Timer_A, Timers TA0, TA1, and TA2
    28. 8.28 Timer_B, Timer TB0
    29. 8.29 Battery Backup
    30. 8.30 USCI (UART Mode)
    31. 8.31 USCI (SPI Master Mode)
    32. 8.32 USCI (SPI Slave Mode)
    33. 8.33 USCI (I2C Mode)
    34. 8.34 12-Bit ADC, Power Supply and Input Range Conditions
    35. 8.35 12-Bit ADC, Timing Parameters
    36. 8.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    37. 8.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    38. 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 8.40 REF, External Reference
    41. 8.41 REF, Built-In Reference
    42. 8.42 12-Bit DAC, Supply Specifications
    43. 8.43 12-Bit DAC, Linearity Specifications
    44. 8.44 12-Bit DAC, Output Specifications
    45. 8.45 12-Bit DAC, Reference Input Specifications
    46. 8.46 12-Bit DAC, Dynamic Specifications
    47. 8.47 12-Bit DAC, Dynamic Specifications (Continued)
    48. 8.48 Comparator_B
    49. 8.49 Ports PU.0 and PU.1
    50. 8.50 LDO-PWR (LDO Power System)
    51. 8.51 Flash Memory
    52. 8.52 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  Memory
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power-Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 ADC12_A
      17. 9.12.17 DAC12_A
      18. 9.12.18 CRC16
      19. 9.12.19 Voltage Reference (REF) Module
      20. 9.12.20 LDO and PU Port
      21. 9.12.21 Embedded Emulation Module (EEM)
      22. 9.12.22 Peripheral File Map
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 9.13.13 Port PU (PU.0 and PU.1) Ports
      14. 9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  支持资源
    7. 10.7  Trademarks
    8. 10.8  静电放电警告
    9. 10.9  Export Control Notice
    10. 10.10 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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订购信息

8.31 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-11 and Figure 8-12)
PARAMETERTEST CONDITIONSVCCMINMAXUNIT
fUSCIUSCI input clock frequencySMCLK or ACLK,
Duty cycle = 50% ±10%		fSYSTEMMHz
tSU,MISOMI input data setup timePMMCOREV = 01.8 V55ns
3 V38
PMMCOREV = 32.4 V30
3 V25
tHD,MISOMI input data hold timePMMCOREV = 01.8 V0ns
3 V0
PMMCOREV = 32.4 V0
3 V0
tVALID,MOSIMO output data valid time(2)UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0		1.8 V20ns
3 V18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3		2.4 V16
3 V15
tHD,MOSIMO output data hold time(3)CL = 20 pF, PMMCOREV = 01.8 V–10ns
3 V–8
CL = 20 pF, PMMCOREV = 32.4 V–10
3 V–8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-11 and Figure 8-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 8-11 and Figure 8-12.
GUID-2DDB944D-5009-4555-AC31-EBC13A2F8C0F-low.gifFigure 8-11 SPI Master Mode, CKPH = 0
GUID-CE2819E7-9565-4779-9EF7-AB6E0F9F10FB-low.gifFigure 8-12 SPI Master Mode, CKPH = 1