ZHCSTV0L November   2001  – February 2025 LP2992

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
        1. 6.3.3.1 Current Limit (Legacy Chip)
        2. 6.3.3.2 Current Limit (New Chip)
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Estimating Junction Temperature
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Noise Bypass Capacitor (CBYPASS)
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Recommended Capacitor Types
        1. 7.1.5.1 Recommended Capacitors (Legacy Chip)
          1. 7.1.5.1.1 Tantalum Capacitors (Legacy Chip)
        2. 7.1.5.2 Recommended Capacitors (New Chip)
      6. 7.1.6 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON/OFF Operation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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7.2.3 Application Curves

LP2992 Load Transient Response for Legacy Chip
 
Figure 7-3 Load Transient Response for Legacy Chip
LP2992 Load Transient Response for Legacy Chip
 
Figure 7-5 Load Transient Response for Legacy Chip
LP2992 Line Transient Response for Legacy Chip
 
 
Figure 7-7 Line Transient Response for Legacy Chip
LP2992 Line Transient Response for Legacy Chip
 
 
Figure 7-9 Line Transient Response for Legacy Chip
LP2992 Turn-on Time for Legacy Chip
 
Figure 7-11 Turn-on Time for Legacy Chip
LP2992 Turn-on Time for Legacy Chip
 
Figure 7-13 Turn-on Time for Legacy Chip
LP2992 Load Transient for New Chip
dI/dt = 1 A/μ
Figure 7-4 Load Transient for New Chip
LP2992 Load Transient Response for New Chip
dI/dt = 1 A/μ
Figure 7-6 Load Transient Response for New Chip
LP2992 Line Transient Response for New Chip
VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA,
dV/dt = 1 V/μ
Figure 7-8 Line Transient Response for New Chip
LP2992 Line Transient Response for New Chip
VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA,
dV/dt = 1 V/μ
Figure 7-10 Line Transient Response for New Chip
LP2992 Turn-on Time for New Chip
 
Figure 7-12 Turn-on Time for New Chip
LP2992 Turn-on Time for New Chip
COUT = 4.7 μF
Figure 7-14 Turn-on Time for New Chip