at TA = 25°C, VS
= 5V (±2.5V) to 10V (±5V), OUTA RL = 10kΩ connected to VS / 2,
OUTB RL = 2kΩ connected to VS / 2,
VCM =
VREFA = VS / 2, VREFGND = VS–,
II1 = 1µA, and II2 = 1µA (unless otherwise noted)
| VS = 5V (±2.5V), n
= 300, 10µV bin width |
Figure 5-1 Auxiliary-Amplifier Offset-Voltage Distribution
| VS = 5V (±2.5V), n
= 300, 0.5mV bin width |
Figure 5-3 Difference-Amplifier Output-Offset Voltage Distribution
| VS = 5V (±2.5V), n
= 300, 0.05% bin width |
Figure 5-5 Scaling-Factor Error Distribution
Figure 5-7 Output Voltage vs I1 Current
Figure 5-9 Output Voltage vs Input Currents
| Without calibration for scaling
factor error or VOS |
Figure 5-11 Average Total Error vs I1 Current
Figure 5-13 Logarithmic-Conformity Error Distribution vs I1 Current
Figure 5-15 Logarithmic-Conformity Error Distribution vs Input Current
| Using 1nA–1mA best-fit line
for scaling-factor error correction |
Figure 5-17 Seven-Decade Logarithmic Conformity Error vs I1 Current
Figure 5-19 Logarithmic-Amplifier Offset vs I1 Current
Figure 5-21 Auxiliary-Amplifier Small-Signal Step Response
Figure 5-23 Step
Response for Various CIN
Figure 5-25 Step
Response for Decade Steps, Rising
Figure 5-27 Step
Response for Two-Decade Step
Figure 5-29 Small-Signal II1 AC Response
Figure 5-31 Difference-Amplifier Offset vs Temperature
Figure 5-33 Auxiliary-Amplifier Offset vs Temperature
Figure 5-35 IREF vs Temperature
Figure 5-37 IREF Line Regulation
| Normalized to value at
TA = 25°C, IVREF = 1mA, n =
7 |
Figure 5-39 VREF165 vs Temperature
Figure 5-41 VREF165 Load Regulation
| VS = 5V (±2.5V),
VIBIAS = (VS+) – 1V, mean of n
= 32 samples |
Figure 5-43 IBIAS Ratio vs I1 Current
| VS = 5V (±2.5V),
sourcing |
Figure 5-45 Auxiliary-Amplifier Output Voltage vs Output Current
Figure 5-47 Auxiliary-Amplifier Output Voltage vs Output Current
Figure 5-49 VS+
Current vs I1 Current
| IOUTA =
IOUTB = 0mA, IBIAS floating, n =
30 |
Figure 5-51 VS+ Current vs Temperature
| VS = 10V (±5V), n
= 300, 10µV bin width |
Figure 5-2 Auxiliary-Amplifier Offset-Voltage Distribution
| VS = 10V (±5V), n
= 300, 0.5mV bin width |
Figure 5-4 Difference-Amplifier Output-Offset Voltage Distribution
| VS = 10V (±5V), n
= 300, 0.05% bin width |
Figure 5-6 Scaling-Factor Error Distribution
Figure 5-8 Output Voltage vs I2 Current
| Includes log conformity
error |
Figure 5-10 Scaling Factor Error vs I1 Current
| Without calibration for scaling
factor error or VOS |
Figure 5-12 Average Total Error vs I1 Current
Figure 5-14 Logarithmic-Conformity Error Distribution vs I1 Current
| Using 1nA–100µA best-fit line
for scaling-factor error correction |
Figure 5-16 Six-Decade Logarithmic Conformity Error vs I1 Current
| Using 1nA–10mA best-fit line
for scaling-factor error correction |
Figure 5-18 Eight-Decade Logarithmic Conformity Error vs I1 Current
Figure 5-20 Logarithmic-Amplifier Offset vs I2 Current
Figure 5-22 Auxiliary-Amplifier Small-Signal Step Response
Figure 5-24 Step
Response for Various COUT
Figure 5-26 Step
Response for Decade Steps, Falling
Figure 5-28 Voltage-Reference-Noise Spectral Density
Figure 5-30 Small-Signal II2 AC Response
Figure 5-32 Difference-Amplifier Offset vs Temperature
Figure 5-34 Auxiliary-Amplifier Offset vs Temperature
Figure 5-36 IREF vs Temperature
Figure 5-38 IREF Line Regulation
| Normalized to value at
TA = 25°C, IVREF = 1mA, n =
15 |
Figure 5-40 VREF25 vs Temperature
Figure 5-42 VREF25 Load Regulation
| VS = 10V (±5V),
VIBIAS = (VS+) – 1V, mean of n
= 32 samples |
Figure 5-44 IBIAS Ratio vs I1 Current
Figure 5-46 Auxiliary-Amplifier Output Voltage vs Output Current
Figure 5-48 Auxiliary-Amplifier Output Voltage vs Output Current
Figure 5-50 VS–
Current vs I1 Current