ZHCSLT9B March 2022 – July 2022 LMK5B33216
PRODUCTION DATA
There are one or more output dividers after each output mux. Each channel in OUT[0:1] has an individual 12-bit channel divider cascaded an optional 20-bit SYSREF divider. Each channel in OUT[2:3] and OUT[14:15] has an individual 12-bit output divider. The OUT[4:5], OUT[6:7], OUT[8:9], OUT[10:11], and OUT[12:13] channels each have a single 12-bit output divider cascaded with an optional SYSREF divider. The output dividers are used to generate the final clock output frequency from the source selected by the output mux.
The OUT0 or OUT1 channel combines a 12-bit output channel divider (CD) and a 20-bit SYSREF divider to support output frequencies from 1 Hz (1 PPS) to 1250 MHz. From VCO to output, the total divide value is the product of the PLL post-divider (P), output channel divider (CD)and SYSREF divider (SD) values (P × CD × SD).
For example, with the APLL3 post-divider bypassed each 12-bit channel divider (CD) supports output frequencies from 100 kHz to 1250 MHz (or up to the maximum frequency supported by the configured output driver type). It is possible to then cascade the SYSREF divider (SD) to achieve lower clock frequencies down to 1 Hz (1 PPS).
Each output divider is powered from the same VDDO_x supply used for the clock output drivers. The output divider can be powered down if not used to save power. For each output group in OUT[2:3], OUT[4:5], OUT[6:7], OUT[8:9], OUT[10:11], OUT[12:13], or OUT[14:15], the output divider is automatically powered down when both output drivers are disabled. For OUT0 or OUT1 channel, the output divider is automatically powered down when its output driver is disabled.