SNVS397F September   2005  – December 2025 LM5005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Shutdown and Standby
      3. 6.3.3 Oscillator and Synchronization Capability
      4. 6.3.4 Error Amplifier and PWM Comparator
      5. 6.3.5 RAMP Generator
      6. 6.3.6 Current Limit
      7. 6.3.7 Soft-Start Capability
      8. 6.3.8 MOSFET Gate Driver
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Light-Load Operation
      4. 6.4.4 Thermal Shutdown Protection
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reducing Bias Power Dissipation
      2. 7.1.2 Input Voltage UVLO Protection
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  Frequency Set Resistor (RT)
        3. 7.2.2.3  Inductor (LF)
        4. 7.2.2.4  Ramp Capacitor (CRAMP)
        5. 7.2.2.5  Output Capacitors (COUT)
        6. 7.2.2.6  Schottky Diode (DF)
        7. 7.2.2.7  Input Capacitors (CIN)
        8. 7.2.2.8  VCC Capacitor (CVCC)
        9. 7.2.2.9  Bootstrap Capacitor (CBST)
        10. 7.2.2.10 Soft Start Capacitor (CSS)
        11. 7.2.2.11 Feedback Resistors (RFB1 and RFB2)
        12. 7.2.2.12 RC Snubber (RS and CS)
        13. 7.2.2.13 Compensation Components (RC1, CC1, CC2)
        14. 7.2.2.14 Bill of Materials
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout for EMI Reduction
        2. 7.4.1.2 Thermal Design
        3. 7.4.1.3 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
        1. 8.3.1.1 PCB Layout Resources
        2. 8.3.1.2 Thermal Design Resources
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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7.1.2 Input Voltage UVLO Protection

The SD input supports adjustable input voltage undervoltage lockout (UVLO) with hysteresis for application specific power-up and power-down requirements. SD connects to a comparator-based input referenced to a 1.225V band-gap voltage with 100mV hysteresis. Use an external logic signal to drive the SD input to toggle the output ON and OFF and for system sequencing or protection.

LM5005 Programmable Input Voltage UVLO With HysteresisFigure 7-3 Programmable Input Voltage UVLO With Hysteresis

If the SD pin is not used, leave the pin as open circuit as the pin is pulled high by an internal 5µA current source. This allows self-start-up of the LM5005 when VCC is within its valid operating range above its UVLO threshold. However, Figure 7-3 shows that many applications benefit from using a resistor divider RUV1 and RUV2 to establish a precision input voltage UVLO level.

VIN(on) functions as the input voltage turnon threshold and VIN(off) functions as the input voltage thresholds. Select the UVLO resistors using Equation 7 and Equation 8.

Equation 7. R U V 1 = V I N o f f × 1.225 V 1.125 V - V I N o n 5 μ A
Equation 8. R U V 2 = R U V 1 × 1.225 V V I N o n - 1.225 V + 5 μ A × R U V 1

An optional capacitor CUV in parallel with RUV2 provides filtering for the divider. If the input UVLO level is set at a low input voltage, it is possible that the maximum SD pin voltage of 7V could be exceeded at the higher end of the input voltage operating range. In this case, use a small 6.2V Zener diode clamp from SD to AGND so that the maximum SD operating voltage is never exceeded.