SNVS397F September   2005  – December 2025 LM5005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Shutdown and Standby
      3. 6.3.3 Oscillator and Synchronization Capability
      4. 6.3.4 Error Amplifier and PWM Comparator
      5. 6.3.5 RAMP Generator
      6. 6.3.6 Current Limit
      7. 6.3.7 Soft-Start Capability
      8. 6.3.8 MOSFET Gate Driver
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Light-Load Operation
      4. 6.4.4 Thermal Shutdown Protection
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reducing Bias Power Dissipation
      2. 7.1.2 Input Voltage UVLO Protection
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  Frequency Set Resistor (RT)
        3. 7.2.2.3  Inductor (LF)
        4. 7.2.2.4  Ramp Capacitor (CRAMP)
        5. 7.2.2.5  Output Capacitors (COUT)
        6. 7.2.2.6  Schottky Diode (DF)
        7. 7.2.2.7  Input Capacitors (CIN)
        8. 7.2.2.8  VCC Capacitor (CVCC)
        9. 7.2.2.9  Bootstrap Capacitor (CBST)
        10. 7.2.2.10 Soft Start Capacitor (CSS)
        11. 7.2.2.11 Feedback Resistors (RFB1 and RFB2)
        12. 7.2.2.12 RC Snubber (RS and CS)
        13. 7.2.2.13 Compensation Components (RC1, CC1, CC2)
        14. 7.2.2.14 Bill of Materials
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout for EMI Reduction
        2. 7.4.1.2 Thermal Design
        3. 7.4.1.3 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
        1. 8.3.1.1 PCB Layout Resources
        2. 8.3.1.2 Thermal Design Resources
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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7.2.2.13 Compensation Components (RC1, CC1, CC2)

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current-mode control is the ability to close the loop with only two feedback components, RC1 and CC1. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM5005 is calculated with Equation 17.

Equation 17. G A I N M O D - D C = G m M O D × R L O A D = 2 × R L O A D

The dominant low-frequency pole of the modulator is determined by the load resistance, RLOAD, and the output capacitance, COUT. Calculate the corner frequency of this pole with Equation 18.

Equation 18. f p M O D = 1 2 π × R L O A D × C O U T

For RLOAD = 5Ω and COUT = 177 µF, then fp(MOD) = 180Hz

Equation 19. GAINMOD-DC=2A/V×5Ω=10=20dB

For this design example given RLOAD = 5Ω and COUT = 177 µF, Figure 7-6 shows the experimentally measured modulator gain versus frequency characteristic.

LM5005 PWM Modulator Gain and Phase PlotFigure 7-6 PWM Modulator Gain and Phase Plot

Components RC1 and CC1 configure the error amplifier as a Type-II configuration, giving a pole at the origin and a zero at:

Equation 20. fZ=1÷2πRC1CC1

The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a stable loop with 90° of phase margin.

For the design example, select a target loop bandwidth (crossover frequency) of 20kHz. Place the compensator zero frequency, fZ, an order of magnitude less than the target crossover frequency. This constrains the product of RC1 and CC1 for a desired compensation network zero frequency to be less than 2kHz. Increasing RC1 while proportionally decreasing CC1 increases the error amp gain. Conversely, decreasing RC1 while proportionally increasing CC1, decreases the error amp gain. Select RC1 of 49.9kΩ and CC1 of 10nF. These values configure the compensation network zero at 320Hz. The compensator gain at frequencies greater than fZ is RC1 / RFB1, which is approximately 20dB.

Figure 7-7 shows the compensator bode plot. The overall loop is predicted as the sum (in dB) of the modulator gain and the compensator gain as shown in Figure 7-8.

LM5005 Compensator Gain and Phase PlotFigure 7-7 Compensator Gain and Phase Plot
LM5005 Overall Loop Gain and Phase PlotFigure 7-8 Overall Loop Gain and Phase Plot

If a network analyzer is available, measure the modulator gain and configure the compensator gain for the desired loop transfer function. If a network analyzer is not available, design the compensation components of the error amplifier using the guidelines provided. Perform step-load transient tests to verify acceptable performance. The step load goal is minimum overshoot with a damped response. Add a capacitor CC2 to the compensation network to decrease noise susceptibility of the error amplifier. Verify that the value of CC2 is sufficiently small, because the addition of this capacitor adds a pole in the compensator transfer function. Verify that the pole is well beyond the loop crossover frequency. A good approximation of the location of the pole added by CC2 is Equation 21.

Equation 21. f p 2 = f Z × C C 1 ÷ C C 2

An alternative method to decrease the error amplifier noise susceptibility is to connect a capacitor from COMP to AGND. When using this method, establish that the capacitance of CC2 does not exceed 100pF.