SNVSA38 November   2014 LM3281

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Small Solution Size
      2. 7.3.2  Automatic Analog Bypass with Low Dropout
      3. 7.3.3  Low IQ
      4. 7.3.4  Forced PWM Operation
      5. 7.3.5  High Maximum Current
      6. 7.3.6  High-Capacitance Load and Line Transient Performance
      7. 7.3.7  Soft Start
      8. 7.3.8  Thermal Overload Protection
      9. 7.3.9  Current Limit
      10. 7.3.10 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Forced PWM (FPWM) Mode
      3. 7.4.3 Analog Bypass Mode
      4. 7.4.4 ECO (Economy) Mode
      5. 7.4.5 Shutdown Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Suggested Passive Components
          1. 8.2.1.1.1 LM3281 Inductor Selection
          2. 8.2.1.1.2 Total Effective Output Capacitance (COUT + CLOAD1 + CLOAD2)
          3. 8.2.1.1.3 LM3281 Capacitor (CIN and COUT) Selection
          4. 8.2.1.1.4 Recommended Load Bypass Capacitors (CLOAD1 and CLOAD2)
          5. 8.2.1.1.5 Alternate Output Capacitor Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 COUT-to-CLOAD Inductance
      2. 10.1.2 LM3281-to-CIN Inductance
    2. 10.2 Layout Example
    3. 10.3 DSBGA Package Assembly And Use
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

Optimal LM3281 performance is realized when two important layout considerations are observed. TI-provided layout guidance in this section illustrates best practices, and a customer layout review with the TI applications team will ensure best performance is achieved.

10.1.1 COUT-to-CLOAD Inductance

Minimize inductance in the path between LM3281 COUT capacitor and the load bypass capacitors CLOAD1 and CLOAD2 for best performance. Total power path inductance from the LM3281 output to the load (including vias and traces) should target < 1 nH and must not exceed 2 nH.

10.1.2 LM3281-to-CIN Inductance

Minimize inductance between LM3281 pins (VIN, GND) and the LM3281 input bypass capacitor CIN for best performance. The LM3281 device and CIN capacitor should be placed to permit shortest possible top-metal routing for these connections.

Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads which can result in erratic or degraded performance of the converter. By its very nature, any switching converter generates electrical noise, and the circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3281, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following general guidelines are offered to help mitigate EMI and facilitate good layout design.

  • Place the LM3281 switcher, its input capacitor, and output filter inductor and capacitor close together, and make the Inter-connecting traces as short as possible.
  • Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3281 and the inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3281 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
  • Make the current loop area(s) as small as possible.
  • Reduce the amount of switching current that circulates through the ground plane: Connect the ground bump of the LM3281 and its input filter capacitor together using generous component-side copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane (if one is used) with multiple vias. These multiple vias help to minimize ground bounce at the LM3281 by giving it a low-impedance ground connection.
  • Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when needed.
  • Route noise sensitive traces, such as the voltage feedback path, as directly as possible from the switcher FB pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the power components.
  • Take advantage of the inherent inductance of circuit traces to reduce coupling among various function blocks on the board, by way of the power supply traces.

10.2 Layout Example

Layout.gifFigure 26. LM3281 Layout Example

10.3 DSBGA Package Assembly And Use

Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in Texas Instruments Application Note 1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with DSBGA package should be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this.

The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA devices are sensitive to light (in the red and infrared range) shining on the package's exposed die edges.