ZHCSH33Z September   1997  – April 2025 LM317

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information (Legacy Chip)
    5. 6.5 Thermal Information (New Chip)
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 NPN Darlington Output Drive
      2. 7.3.2 Overload Block
      3. 7.3.3 Programmable Feedback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Operation With Low Input Voltage
      3. 7.4.3 Operation at Light Loads
      4. 7.4.4 Operation In Self Protection
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1  0V to 30V Regulator Circuit
      2. 8.3.2  Adjustable Regulator Circuit With Improved Ripple Rejection
      3. 8.3.3  Precision Current-Limiter Circuit
      4. 8.3.4  Tracking Preregulator Circuit
      5. 8.3.5  1.25V to 20V Regulator Circuit With Minimum Program Current
      6. 8.3.6  Battery-Charger Circuit
      7. 8.3.7  50mA, Constant-Current, Battery-Charger Circuit
      8. 8.3.8  Slow Turn-On 15V Regulator Circuit
      9. 8.3.9  AC Voltage-Regulator Circuit
      10. 8.3.10 Current-Limited 6V Charger Circuit
      11. 8.3.11 Adjustable 4A Regulator Circuit
      12. 8.3.12 High-Current Adjustable Regulator Circuit
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Considerations
          1. 8.5.1.1.1 Heat Sink Requirements
          2. 8.5.1.1.2 Heat Sinking Surface-Mount Packages
            1. 8.5.1.1.2.1 Heatsinking the SOT-223 (DCY) Package
            2. 8.5.1.1.2.2 Heat Sinking the TO-263 (KTT) Package
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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6.6 Electrical Characteristics

some specifications apply over the full operating temperature range as noted; unless otherwise specified, TJ = 25°C, VIN − VOUT = 5V, and IOUT = 10mA(1)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
Reference voltage TJ = 25°C 1.25 V
3V ≤ (VIN − VOUT) ≤ 40V,
10mA ≤ IOUT ≤ 1500mA, PD ≤ 20W		 1.2 1.25 1.3
Line regulation(2) 3V ≤ (VIN − VOUT) ≤ 40V(4) TJ = 25°C 0.01 0.04 %/V
(over full operating temperature range) 0.02 0.07
Load regulation Legacy chip IO = 10mA to 1500mA, CADJ = 10μF(3), TJ = 25°C VO ≤ 5V 25 mV
VO ≥ 5V 0.1 0.5 %VO
IO = 10mA to 1500mA, TJ = 0°C to 125°C VO ≤ 5V 20 70 mV
VO ≥ 5V 0.3 1.5 %VO
New chip 10mA ≤ IOUT ≤ IMAX(5) TJ = 25°C 0.1 0.5
(over full operating temperature range) 0.3 1.5
Thermal regulation 20ms pulse 0.04 0.07 %/W
Adjustment pin current Over full operating temperature range 50 100 μA
Adjustment pin current change 10mA ≤ IOUT ≤ IMAX(4)
3V ≤ (VIN − VOUT) ≤ 40V		 Over full operating temperature range 0.2 5 μA
Temperature stability Legacy chip TMIN ≤ TJ ≤ TMAX Over full operating temperature range 0.7 %VO
New chip 1%
Minimum load current (VIN − VOUT) = 40V Over full operating temperature range 3.5 10 mA
Current limit (VIN − VOUT) ≤ 15V  PD < PMAX(3) 1.5 2.2 A
(VIN − VOUT) = 40V PD < PMAX(3), TJ = 25°C 0.15 0.4
RMS output noise, % of VOUT 10Hz ≤ f ≤ 10kHz 0.003 %
Ripple rejection ratio Legacy chip VOUT = 10V, f = 120Hz, CADJ = 0μF(4) 57 dB
VOUT = 10V, f = 120Hz, CADJ = 10μF(4) 62 64
New chip VOUT = 10V, f = 120Hz, CADJ = 0μF (over full operating temperature range) 65
VOUT = 10V, f = 120Hz, CADJ = 10μF (over full operating temperature range) 66 80
Long-term stability TJ = 25°C 0.3 1 %/1k hr
(1) For the legacy chip (unless otherwise noted), the following test conditions apply: |VI – VO| = 5V, IOMAX = 1.5A, and TJ = 0°C to 125°C. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
(2) For the legacy chip, line regulation is expressed as the percentage change in output voltage per 1V change at the input.
(3) For the legacy chip, maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA) / RθJA. Operating at the absolute maximum TJ of 150°C potentially affects reliability.
(4) For the legacy chip, CADJ is connected between the ADJUST pin and GND.
(5) For the new chip, regulation is measured at a constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage resulting from heating effects are covered under the specifications for thermal regulation.