ZHCS529I January   2007  – April 2025 LM25574

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High Voltage Start-Up Regulator
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown and Standby Mode
      2. 6.4.2 Oscillator and Sync Capability
      3. 6.4.3 Error Amplifier and PWM Comparator
      4. 6.4.4 Ramp Generator
      5. 6.4.5 Maximum Duty Cycle and Input Drop-out Voltage
      6. 6.4.6 Current Limit
      7. 6.4.7 Soft-Start
      8. 6.4.8 Boost Pin
      9. 6.4.9 Thermal Protection
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Schematic for High Frequency (1MHz) Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Custom Design With WEBENCH® Tools
        2. 7.2.3.2  External Components
        3. 7.2.3.3  R3 -RT Resistor
        4. 7.2.3.4  L1-Inductor
        5. 7.2.3.5  C3 (CRAMP)
        6. 7.2.3.6  C9-Output Capacitor
        7. 7.2.3.7  C1-Input Capacitor
        8. 7.2.3.8  C8- VCC Capacitor
        9. 7.2.3.9  C7- BST capacitor
        10. 7.2.3.10 C4 - SS Capacitor
        11. 7.2.3.11 R5, R6 - Feedback Resistor
        12. 7.2.3.12 R1, R2, C2 - SD Pin Components
        13. 7.2.3.13 R4, C5, C6 - Compensation Components
        14. 7.2.3.14 Bias Power Dissipation Reduction
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout and Thermal Considerations
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Developmental Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Ramp Generator

The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the buck switch current. This switch current corresponds to the positive slope portion of the output inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the current measurement can introduce significant propagation delays. The filtering, blanking time and propagation delay limit the minimum achievable pulse width. In applications where the input voltage can be relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles is necessary for regulation. The LM25574 uses a unique ramp generator, which does not actually measure the buck switch current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements; a sample and hold DC level and an emulated current ramp.

LM25574 Composition of Current Sense SignalFigure 6-5 Composition of Current Sense Signal

The sample and hold DC level illustrated in Figure 6-5 is derived from a measurement of the re-circulating Schottky diode anode current. The re-circulating diode anode must be connected to the IS pin. The diode current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode current sensing and sample and hold provide the DC level of the reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to AGND and an internal voltage controlled current source. The ramp current source that emulates the inductor current is a function of the Vin and Vout voltages per Equation 2:

Equation 2. IRAMP = (10µ × (Vin – Vout)) + 50µA

Proper selection of the RAMP capacitor depends upon the selected value of the output inductor. The value of CRAMP can be selected from: CRAMP = L × 5 × 10-6, where L is the value of the output inductor in Henrys. With this value, the scale factor of the emulated current ramp is approximately equal to the scale factor of the DC level sample and hold (2.0V / A). The CRAMP capacitor must be located very close to the device and connected directly to the pins of the IC (RAMP and AGND).

For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 50 µA of offset current provided from the emulated current source adds some fixed slope to the ramp signal. In some high output voltage, high duty cycle applications, additional slope can be required. In these applications, a pullup resistor can be added between the VCC and RAMP pins to increase the ramp slope compensation.

For VOUT > 7.5V:

Calculate optimal slope current, IOS = VOUT × 10µA/V.

For example, at VOUT = 10V, IOS = 100µA.

Install a resistor from the RAMP pin to VCC:

RRAMP = VCC / (IOS – 50µA)

LM25574 RRAMP to VCC for VOUT > 7.5VFigure 6-6 RRAMP to VCC for VOUT > 7.5V