SLLS868T September   2007  – April 2017 ISO7240C , ISO7240CF , ISO7240M , ISO7241C , ISO7241M , ISO7242C , ISO7242M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configurations and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: VCC1 and VCC2 at 5-V Operation
    10. 7.10 Supply Current Characteristics: VCC1 and VCC2 at 5-V Operation
    11. 7.11 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    12. 7.12 Supply Current Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    13. 7.13 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    14. 7.14 Supply Current Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    15. 7.15 Electrical Characteristics: VCC1 and VCC2 at 3.3 V Operation
    16. 7.16 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V Operation
    17. 7.17 Switching Characteristics: VCC1 and VCC2 at 5-V Operation
    18. 7.18 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    19. 7.19 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V Operation
    20. 7.20 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
    21. 7.21 Insulation Characteristics Curves
    22. 7.22 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Isolated Data Acquisition System for Process Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Isolated SPI for an Analog Input Module with 16 Inputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Isolated RS-232 Interface
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

Overview

The isolator in Figure 17 is based on a capacitive isolation-barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop the output of which feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, as in the case of a low-frequency signal, the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is required to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

Functional Block Diagram

ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M fbdc_slls868.gif Figure 17. Conceptual Block Diagram of a Digital Capacitive Isolator

Feature Description

The ISO724xx family of devices is available in multiple channel configurations and default output-state options to enable wide variety of application uses. Table 1 lists these device features.

Table 1. Device Features

PRODUCT SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
ISO7240C 25 Mbps ~1.5 V (TTL) 4/0
ISO7240CF 25 Mbps ~1.5 V (TTL)
ISO7240M 150 Mbps VCC/ 2 (CMOS)
ISO7241C 25 Mbps ~1.5 V (TTL) 3/1
ISO7241M 150 Mbps VCC/ 2 (CMOS)
ISO7242C 25 Mbps ~1.5 V (TTL) 2/2
ISO7242M 150 Mbps VCC/ 2 (CMOS)

Device Functional Modes

Table 2 lists the ISO724xx functional modes. Table 3 lists the ISO7240CF functional modes.

Table 2. Device Function Table ISO724x(1)

INPUT VCC OUTPUT VCC INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
PU PU H H or Open H
L H or Open L
X L Z
Open H or Open H
PD PU X H or Open H
PD PU X L Z
X PD X X Undetermined
PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level; Z = High Impedance; Open = Not Connected

Table 3. ISO7240CF Functions Table(1)

VCC1 VCC2 DATA INPUT
(IN)
DISABLE INPUT
(DISABLE)
FAILSAFE CONTROL
(CTRL)
DATA OUTPUT
(OUT)
PU PU H L or Open X H
PU PU L L or Open X L
X PU X H H or Open H
X PU X H L L
PD PU X X H or Open H
PD PU X X L L
X PD X X X Undetermined

Device I/O Schematics

ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M io_sch_lls868.gif Figure 18. Device I/O Schematics