SLLSFC3A March   2020  – December 2021 ISO1640-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6.     Insulation Specifications
    7. 6.6  Safety-Related Certifications
    8. 6.7  Safety Limiting Values
    9. 6.8  Electrical Characteristics
    10. 6.9  Supply Current Characteristics
    11. 6.10 Timing Requirements
    12. 6.11 Switching Characteristics
    13. 6.12 Insulation Characteristics Curves
    14. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Isolation Technology Overview
    4. 8.4 Feature Description
      1. 8.4.1 Hot Swap
      2. 8.4.2 Protection Features
    5. 8.5 Isolator Functional Principle
      1. 8.5.1 Receive Direction (Left Diagram of Figure 1-1 )
      2. 8.5.2 Transmit Direction (Right Diagram of Figure 1-1 )
    6. 8.6 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I2C Bus Overview
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Insulation Lifetime
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT
DW D
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air >8 >4 mm
CPG External Creepage(1) Side 1 to side 2 distance across package surface >8 >4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 >400 V
Material Group According to IEC 60664-1 I II
Overvoltage category Rated mains voltage ≤ 150 VRMS I-IV I-IV
Rated mains voltage ≤ 300 VRMS I-IV I-III
Rated mains voltage ≤ 600 VRMS I-IV n/a
Rated mains voltage ≤ 1000 VRMS I-III n/a
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 637 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; 1500 450 VRMS
DC voltage 2121 637 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7071 4242 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM (8-D qualification)
VTEST = 1.6 × VIOSM (16-DW qualification)		 6250 5000 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤ 5 ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM , tm = 10 s		 ≤ 5 ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM , tm = 1 s		 ≤ 5 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1 MHz 1 1 pF
RIO Insulation resistance, input to output(5) VIO = 500 V,  TA = 25°C > 1012 > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 150°C > 1011 > 1011
VIO = 500 V at  TS = 150°C > 109 > 109
Pollution degree 2 2
Climatic category 40/125/
21		 40/125/
21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) 5000 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these.
(2) ISO164xDW is suitable for safe electrical insulation and ISO164xBD is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.