SLLSFC3A March   2020  – December 2021 ISO1640-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6.     Insulation Specifications
    7. 6.6  Safety-Related Certifications
    8. 6.7  Safety Limiting Values
    9. 6.8  Electrical Characteristics
    10. 6.9  Supply Current Characteristics
    11. 6.10 Timing Requirements
    12. 6.11 Switching Characteristics
    13. 6.12 Insulation Characteristics Curves
    14. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Isolation Technology Overview
    4. 8.4 Feature Description
      1. 8.4.1 Hot Swap
      2. 8.4.2 Protection Features
    5. 8.5 Isolator Functional Principle
      1. 8.5.1 Receive Direction (Left Diagram of Figure 1-1 )
      2. 8.5.2 Transmit Direction (Right Diagram of Figure 1-1 )
    6. 8.6 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I2C Bus Overview
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Insulation Lifetime
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6.8 Electrical Characteristics

over recommended operating conditions, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SIDE 1
VILT1 Voltage input threshold low
(SDA1 and SCL1) 		 480 560 mV
VIHT1 Voltage input threshold high
(SDA1 and SCL1)		 520 620 mV
VHYST1 Voltage input hysteresis VIHT1 – VILT1 50 60 mV
VOL1 Low-level output voltage
(SDA1 and SCL1)		 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA 570 650 710 mV
ΔVOIT1 Low-level output voltage to highlevel input voltage threshold difference, SDA1 and SCL1(1)(2) 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA 50 mV
SIDE 2
VILT2 Voltage input threshold low
(SDA2 and SCL2)		 0.3 × VCC2 0.4 × VCC2 V
VIHT2 Voltage input threshold high
(SDA2 and SCL2)		 0.4 × VCC2 0.5 × VCC2 V
VHYST2 Voltage input hysteresis VIHT2 – VILT2 0.05 × VCC2 V
VOL2 Low-level output voltage
(SDA2 and SCL2)		 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 50 mA 0.4 V
BOTH SIDES
|II| Input leakage currents
(SDA1, SCL1, SDA2, and SCL2)		 VSDA1, VSCL1 = VCC1,
VSDA2, VSCL2 = VCC2		 0.01 10 µA
CI Input capacitance to local ground
(SDA1, SCL1, SDA2, and SCL2)		 VI = 0.4 × sin(2e6*πt) + VDDx / 2 10 pF
CMTI Common-mode transient immunity VCM = 1000 V, see Figure 7-3 50 100 kV/µs
(1) ∆VOIT1 = VOL1 – VIHT1. This value represents the minimum difference between a threshold for the low-level output voltage and a threshold for the high-level input voltage to prevent a permanent latch condition that would otherwise occur with bidirectional communication.
(2) Any supply voltages on either side that are less than the minimum value make sure that the device does a lockout. Both supply voltages that are greater than the maximum value keep the device from a lockout.