ZHCSL04A March 2020 – July 2020 ISO1044
PRODUCTION DATA

VCC2 = 5V, Temp = 25°C, RL = 60 Ω , CL(RXD) = 15pF
Figure 6-3 Side 1 Supply Current vs Datarate.
VCC1 = VCC2 = 5V, RL = 60 Ω, CL(RXD) = 15pF
Figure 6-5 Side 1 Supply Current vs Ambient Temperature.
VCC1 = VCC2 = 5V, Bus Load = 60 Ω || 100 pF, CL(RXD) = 15pF
Figure 6-7 Loop Delay vs Ambient Temperature.
VCC1 = 5V, Temp = 25°C, RL = 60 Ω
Figure 6-9 Dominant state differential output voltage vs Side2 supply voltage.
VCC1 = VCC2 = 5V, RL = 60Ω
Figure 6-11 Dominant timeout vs Ambient Temperature.
Figure 6-13 Glitch Free Power Up on VCC2 – CAN Bus Remains Recessive
Figure 6-15 Typical TXD, RXD, CANH and CANL Waveforms at 500 kbps
VCC1 = 5V, Temp = 25°C, RL = 60 Ω, CL(RXD) = 15pF
Figure 6-4 Side 2 Supply Current vs Datarate.
VCC1 = VCC2 = 5V, RL = 60 Ω, CL(RXD) = 15pF
Figure 6-6 Side 2 Supply Current vs Ambient Temperature.
VCC1 = VCC2 = 5V, RL = 60 Ω
Figure 6-8 Dominant state differential output voltage vs Ambient Temperature.
VCC1 = VCC2 = 5V, TXD = Floating
Figure 6-10 Receiver differential threshold voltage vs Ambient Temperature.
Figure 6-12 Glitch Free Power Up on VCC1 – CAN Bus Remains Recessive
Figure 6-14 Typical TXD, RXD, CANH and CANL Waveforms at 2 Mbps