ZHCSEX8A December   2015  – October 2016 INA300-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Selecting a Current-Sensing Resistor
        1. 7.3.1.1 Selecting a Current-Sensing Resistor: Example
      2. 7.3.2 Setting The Current-Limit Threshold
        1. 7.3.2.1 Resistor-Controlled Current Limit
        2. 7.3.2.2 Voltage Source Controlled Current Limit
      3. 7.3.3 Delay Setting
      4. 7.3.4 Alert Timing Response
      5. 7.3.5 Selectable Hysteresis
      6. 7.3.6 Alert Output
      7. 7.3.7 Noise Adjustment Factor (NAF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Alert Mode
        1. 7.4.1.1 Transparent Output Mode
        2. 7.4.1.2 Latch Output Mode
      2. 7.4.2 Disable Mode
      3. 7.4.3 Input Filtering
      4. 7.4.4 Using the INA300-Q1 With Common-Mode Transients Above 36 V
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Unidirectional Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Operation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Window Comparator
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档 
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

  • The power-supply bypass capacitor must be placed as closely as possible to the supply and ground terminals. The recommended value of this bypass capacitor is 0.1 µF. Additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies.
  • The connection of RLIMIT to the ground terminal must be made as direct as possible to limit additional capacitance on this node. Routing this connection must be limited to the same plane if possible avoiding vias to internal planes. If the routing cannot be made on the same plane and must pass through vias, ensure that a path is routed from the RLIMIT back to the ground terminal and that the RLIMIT is not connected directly to a ground plane.
  • The DELAY terminal must be either connected directly to ground, directly to supply, or left completely floating. Additional external resistors must not be connected to this terminal. If a resistance is required by the application to be placed in series with either the supply or ground connection to the DELAY terminal, this resistance must be limited to 1 kΩ so as to not conflict with the internal level detection circuitry.
  • The HYS terminal must be either connected directly to ground, directly to supply, or left completely floating. Additional external resistors must not be connected to this terminal. If a resistance is required by the application to be placed in series with either the supply or ground connections to the HYS terminal, this resistance must be limited to 1 kΩ so as to not conflict with the internal level detection circuitry.
  • The open-drain output pin is recommended to be pulled up to the supply voltage rail through a 10-kΩ pull-up resistor.

Layout Example

INA300-Q1 ai_recommended-layout_DGS_bos613.gif
NOTE: Connect the limit resistor directly to the GND terminal.
Figure 39. Recommended Layout for VSSOP Package