ZHCSHA7E January   2001  – January 2018 DS92LV040A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化功能图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuits and Timing Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Supply Voltage
        2. 9.2.3.2 Supply Bypass Capacitance
        3. 9.2.3.3 Termination Resistors
        4. 9.2.3.4 Interconnecting Media
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

NJN Package
WQFN (44 Pin)
Top View
DS92LV040A NJN_pin_diagram.gif

Pin Functions

PIN NAMEPIN #INPUT/
OUTPUT		DESCRIPTIONS
DO+/RI+ 14, 16, 19, 21 I/O True Bus LVDS Driver Outputs and Receiver Inputs.
DO−/RI− 13, 15, 18, 20 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
DIN 35, 37, 40, 42 I LVTTL Driver Input. No pull up or pull down is attached to this pin
RO 36, 38, 41, 43 O LVTTL Receiver Output.
RE12 29 I Receiver Enable LVTTL Input (Active Low). This pin, when low, configures receiver outputs, RO1 and RO2 active. When this pin is high, RO1 and RO2 are TRI-STATE. If this pin is floating, a weak current source to VCC causes RO1 and RO2 to be TRI-STATE
RE34 5 I Receiver Enable LVTTL Input (Active Low). This pin, when low, configures receiver outputs, RO3 and RO4 active. When this pin is high, RO3 and RO4 are TRI-STATE. If this pin is floating, a weak current source to VCC causes RO3 and RO4 to be TRI-STATE
DE12 26 I Driver Enable LVTTL Input (Active High). This pin, when high, configures driver outputs, DO1+/RIN1+, DO1−/RIN1− and DO2+/RIN2+, DO2−/RIN2− active. When this pin is low, driver outputs 1 and 2 are TRI-STATE. If this pin is floating, a weak current source to VCC causes driver outputs 1 and 2 to be active
DE34 8 I Driver Enable LVTTL Input (Active High). This pin, when high, configures driver outputs, DO3+/RIN3+, DO3−/RIN3− and DO4+/RIN4+, DO4−/RIN4− active. When this pin is low, driver outputs 3 and 4 are TRI-STATE. If this pin is floating, a weak current source to VCC causes driver outputs 3 and 4 to be active
GND 4, 28, 31, 39 Ground Ground for digital circuitry (must connect to GND on PC board). These pins connected internally.
VCC 3, 6, 30 Power VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally.
AGND 9, 17, 25 Ground Ground for analog circuitry (must connect to GND on PC board). These pins connected internally.
AVCC 7, 10, 22, 27 Power Analog VCC (must connect to VCC on PC board). These pins connected internally.
NC 1, 2, 11, 12, 23, 24, 32, 33, 34, 44 N/A Reserved for future use, leave open circuit.
DAP GND Must connect to GND plane through vias to achieve the theta ja specified under Absolute Maximum Ratings. The DAP (die attach pad) is the heat transfer material that is centered on the bottom of the WQFN package. Refer to application note AN-1187 () for attachment details.