ZHCSFB4A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 支持资源
    4. 7.4 Trademarks
    5. 7.5 静电放电警告
    6. 7.6 术语表
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

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6.1.1 Power-Over-Coax

The DS90UB964-Q1 is designed to support the Power-over-Coax (PoC) method of powering remote sensor systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed digital video data and bidirectional control and diagnostics data transmission. The method uses passive networks or filters that isolate the transmission line from the loading of the DC-DC regulator circuits and their connecting power traces on both sides of the link as shown in Figure 6-1.

GUID-DFEB1749-46A9-47D6-8B25-B3A6C416BE16-low.gifFigure 6-1 Power-over-Coax (PoC) System Diagram

The PoC networks' impedance of ≥ 1kΩ over a specific frequency band is recommended to isolate the transmission line from the loading of the regulator circuits provided good layout practices are followed and the PCB return loss requirements given in Table 6-2 are met. Higher PoC network impedance contributes to favorable insertion loss and return loss characteristics in the high-speed channel. The lower limit of the frequency band is defined as ½ of the frequency of the back channel, fBC. The upper limit of the frequency band is the frequency of the forward high-speed channel, fFC. However, the main criteria that need to be met in the total high-speed channel, which consists of a serializer PCB, a deserializer PCB, and a cable, are the insertion loss and return loss limits defined in the Total Channel Requirements (see Section 5.4.6.1), while the system is under maximum current load and extreme temperature conditions.

Figure 6-2 shows a PoC network recommended for a "2G" FPD-Link III consisting of a DS90UB913A-Q1 or DS90UB933-Q1 serializer and DS90UB964-Q1 with the bidirectional channel operating at the data rate of 2.5Mbps (½ fBC = 1.25MHz) and the forward channel operating at the data rate as high as 1.87Gbps (fFC ≈ 1GHz).

GUID-4E201930-1C72-4F70-8CF9-82FDDD049746-low.gifFigure 6-2 Example Recommended PoC Network for a "2G" FPD-Link III

Table 6-1 lists essential components for this particular PoC network.

Table 6-1 Suggested Components for a "2G" FPD-Link III PoC Network
CountRef DesDescriptionPart NumberMFR
1L1Inductor, 100µH, 0.310Ω max, 710mA MIN (Isat, Itemp)
7.2MHz SRF typ, 6.6mm × 6.6mm, AEC-Q200		MSS7341-104MLCoilcraft
Inductor, 100µH, 0.606Ω max, 750mAMIN (Isat, Itemp)
7.2MHz SRF typ, 6.0mm × 6.0mm, AEC-Q200		NRS6045T101MMGKVTaiyo Yuden
1L2Inductor, 4.7µH, 0.350Ω max, 700mA MIN (Isat, Itemp)
160MHz SRF typ, 3.8mm × 3.8mm, AEC-Q200		1008PS-472KLCoilcraft
Inductor, 4.7µH, 0.130Ω max, 830mA MIN (Isat, Itemp),
70MHz SRF typ, 3.2mm × 2.5mm, General Purpose		CBC3225T4R7MRVTaiyo Yuden
Inductor, 10µH, 0.288Ω max, 530mA MIN (Isat, Itemp)
30MHz SRF min, 3mm × 3mm, AEC-Q200		LQH3NPZ100MJRMurata
1FB1Ferrite Bead, 1500kΩ at 1GHz, 0.5Ω max at DC
500mA at 85°C, SM0603, General Purpose		BLM18HE152SN1Murata
Ferrite Bead, 1500kΩ at 1GHz, 0.5Ω max at DC
500mA at 85°C, SM0603, AEC-Q200		BLM18HE152SZ1Murata

Application report Sending Power over Coax in DS90UB913A Designs (SNLA224) discusses and defines the PoC networks in more detail.

In addition to the PoC network components selection, the placement and layout play a critical role as well.

  • Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as possible. Route the high-speed trace through one of the ferrite bead pads to avoid stubs.
  • Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner planes below the component pads to minimize impedance drop.
  • Consult with connector manufacturer for optimized connector footprint.
  • Use coupled 100Ω differential signal traces from the device pins to the AC-coupling caps. Use 50Ω single-ended traces from the AC-coupling capacitors to the connector.
  • Terminate the inverting signal traces close to the connectors with standard 49.9Ω resistors.

The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer boards are detailed in Table 6-2. The effects of the PoC networks need to be accounted for when testing the traces for compliance to the suggested limits.

Table 6-2 Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks
PARAMETERMINTYPMAXUNIT
LtraceSingle-ended PCB trace length from the device pin to the connector pin5cm
ZtraceSingle-ended PCB trace characteristic impedance455055Ω
ZconConnector (mounted) characteristic impedance405062.5Ω
RLReturn Loss, S11½ fBC < f < 0.1GHz–20dB
0.1GHz < f < 1GHz (f in GHz)–12 + 8 × log(f)dB
1GHz < f < fFC–12dB
ILInsertion Loss, S12f < 0.5GHz–0.35dB
f = 1GHz–0.6dB

The VPOC noise must be kept to 10mVp-p or lower on the source / deserializer side of the system. The VPOC fluctuations on the serializer side, caused by the sensor's transient current draw and the DC resistance of cables and PoC components, must be kept at minimum as well. Increasing the VPOC voltage and adding extra decoupling capacitance (> 10µF) help reduce the amplitude and slew rate of the VPOC fluctuations.