ZHCSKG3B September   2016  – February 2024 DS280DF810

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, Retimer Jitter Specifications
    7. 5.7  Timing Requirements, Retimer Specifications
    8. 5.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 5.9  Recommended SMBus Switching Characteristics (Target Mode)
    10. 5.10 Recommended SMBus Switching Characteristics (Controller Mode)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver and Transmitter
        2. 6.3.1.2 Signal Detect
        3. 6.3.1.3 Continuous Time Linear Equalizer (CTLE)
        4. 6.3.1.4 Variable Gain Amplifier (VGA)
        5. 6.3.1.5 2x2 Cross-Point Switch
        6. 6.3.1.6 Decision Feedback Equalizer (DFE)
        7. 6.3.1.7 Clock and Data Recovery (CDR)
        8. 6.3.1.8 Calibration Clock
        9. 6.3.1.9 Differential Driver with FIR Filter
          1. 6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
          2. 6.3.1.9.2 Output Driver Polarity Inversion
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
    4. 6.4 Device Functional Modes
      1. 6.4.1 Supported Data Rates
      2. 6.4.2 SMBus Controller Mode
      3. 6.4.3 42
      4. 6.4.4 Device SMBus Address
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Backplane and Mid-Plane Reach Extension Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Front-Port Jitter Cleaning Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABW|135
  • ABV|135
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.3.1.2 Signal Detect

The DS280DF810 receiver contains a signal detect circuit. The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high-speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to automatically power on or off the rest of the high speed data path depending on the presence of an input signal. The signal detect block can be manually controlled in the SMBus channel registers. This can be useful if it is desired to manually force channels to be disabled. For information on how to manually operate the signal detect circuit refer to the DS280DF810 Programming Guide.