ZHCSME1C August   2018  – June 2021 DS250DF230

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
        1. 8.3.7.1 CDR Bypass (Raw) Mode
        2. 8.3.7.2 CDR Fast Lock Mode
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
        3. 8.3.9.3 Slow Slew Rate
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye-Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-Plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14术语表
  15. 15Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

8.4.1 Supported Data Rates

The DS250DF230 supports a wide range of input data rates, including divide-by-2 and divide-by-4 sub-rates. The supported data rates are listed in Table 8-5.

Table 8-5 Supported Data Rates
DATA RATE RANGE DIVIDER CDR MODE COMMENT
MIN MAX
≥ 19.6 Gbps ≤ 25.8 Gbps 1 Enabled
> 12.9 Gbps <19.6 Gbps N/A Bypassed Output jitter will be higher with CDR bypassed.
≥ 9.8 Gbps ≤ 12.9 Gbps 2 Enabled
> 6.45 Gbps < 9.8 Gbps N/A Bypassed Output jitter will be higher with CDR bypassed.
≥ 4.9 Gbps 6.45 ≤ Gbps 4 Enabled
< 4.9 Gbps N/A Bypassed Output jitter will be higher with CDR bypassed.

The device can be configured to operate at different standard data rates by programming the Rate/Sub-Rate register Reg_2F[7:4], For more information on data rate programming, refer to the DS2x0DF810, DS250DFx10, DS250DF230 Programmer's Guide.

Table 8-6 Rate/Sub-Rate Table(1)
RATE Reg_0x2F[7:4]StandardInput Data Rates [Gbps]Recovered Clock Frequency [MHz]
0CPRI Option 912.1651230.72
1CPRI Option 79.8304030.72
2CPRI Option 810.1376030.72
3CPRI Option 1024.3302430.72
4CPRI Option 54.9152030.72
5 (Default)100GbE25.7812532.2265625
6100GbE/ 40GbE/ 10GbE25.7812532.2265625
10.3125032.2265625
740GbE/ 10GbE10.3125032.2265625
8CPRI Option 66.1440030.72
(1) This table is valid only when the calibration clock is 30.72-MHz. Refer to the DS2x0DF810, DS250DFx10, DS250DF230 Programmer's Guide for more information.