ZHCSND1A November   2020  – May 2022 DRV8434

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 引脚功能
  6. 6 规格
    1. 6.1 绝对最大额定值
    2. 6.2 ESD 等级
    3. 6.3 建议运行条件
    4. 6.4 热性能信息
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
      1. 6.6.1 典型特性
  7. 7 详细说明
    1. 7.1 概述
    2. 7.2 功能模块图
    3. 7.3 特性说明
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 峰值电流额定值
        2. 7.3.1.2 均方根电流额定值
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  电流调节
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 上升和下降电流阶段均为混合衰减
        4. 7.3.6.4 Smart tune Dynamic Decay
        5. 7.3.6.5 智能调优纹波控制
        6. 7.3.6.6 PWM 关断时间
        7. 7.3.6.7 消隐时间
      7. 7.3.7  电荷泵
      8. 7.3.8  线性稳压器
      9. 7.3.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
        1. 7.3.9.1 nFAULT 引脚
      10. 7.3.10 保护电路
        1. 7.3.10.1 VM 欠压锁定 (UVLO)
        2. 7.3.10.2 VCP 欠压锁定 (CPUV)
        3. 7.3.10.3 过流保护 (OCP)
          1. 7.3.10.3.1 锁存关断
          2. 7.3.10.3.2 自动重试
        4. 7.3.10.4 开路负载检测 (OL)
        5. 7.3.10.5 热关断 (OTSD)
          1. 7.3.10.5.1 锁存关断
          2. 7.3.10.5.2 自动重试
        6.       Fault Condition Summary
    4. 7.4 器件功能模式
      1. 7.4.1 睡眠模式 (nSLEEP = 0)
      2.      52
      3. 7.4.2 禁用模式（nSLEEP = 1，ENABLE = 0）
      4. 7.4.3 工作模式（nSLEEP = 1，ENABLE = Hi-Z/1）
      5. 7.4.4 nSLEEP 复位脉冲
      6.      功能模式汇总
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 电流调节
        3. 8.2.2.3 衰减模式
        4. 8.2.2.4 应用曲线
        5. 8.2.2.5 Thermal Application
          1. 8.2.2.5.1 Power Dissipation
          2. 8.2.2.5.2 Conduction Loss
          3. 8.2.2.5.3 Switching Loss
          4. 8.2.2.5.4 Power Dissipation Due to Quiescent Current
          5. 8.2.2.5.5 Total Power Dissipation
          6. 8.2.2.5.6 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 大容量电容
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD)
IVM VM operating supply current ENABLE = 1, nSLEEP = 1, No motor load 5 6.5 mA
IVMQ VM sleep mode supply current nSLEEP = 0 2 4 μA
tSLEEP Sleep time nSLEEP = 0 to sleep-mode

120

 μs
tRESET nSLEEP reset pulse nSLEEP low to clear fault

20

40

 μs
tWAKE Wake-up time nSLEEP = 1 to output transition 0.8 1.2 ms
tON Turn-on time VM > UVLO to output transition 0.8 1.2 ms

tEN

Enable time

ENABLE = 0/1 to output transition

5

 μs
VDVDD Internal regulator voltage No external load, 6

V < VVM < 48V

 4.75 5 5.25 V
No external load,

VVM = 4.5V

4.2

4.35

V
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage 6 V < VVM < 48 V VVM + 5 V
f(VCP) Charge pump switching frequency VVM > UVLO; nSLEEP = 1 360 kHz
LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP)
VIL Input logic-low voltage 0 0.6 V
VIH Input logic-high voltage 1.5 5.5 V
VHYS Input logic hysteresis 150 mV
IIL Input logic-low current VIN = 0 V –1 1 μA
IIH Input logic-high current VIN = 5 V 100 μA
TRI-LEVEL INPUTS (M0, DECAY0, DECAY1, ENABLE)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 Input Hi-Z voltage Hi-Z 1.8 2 2.2 V
VI3 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IO Output pull-up current 10 μA
QUAD-LEVEL INPUTS (M1, TOFF)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 330kΩ ± 5% to GND 1 1.25 1.4 V
VI3 Input Hi-Z voltage Hi-Z 1.8 2 2.2 V
VI4 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IIL Output pull-up current 10 μA
CONTROL OUTPUTS (nFAULT)
VOL Output logic-low voltage IO = 5 mA 0.5 V
IOH Output logic-high leakage –1 1 μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON) High-side FET on resistance TJ = 25 °C, IO = -1 A 165 200 mΩ
TJ = 125 °C, IO = -1 A 250 300 mΩ
TJ = 150 °C, IO = -1 A 280 350 mΩ
RDS(ON) Low-side FET on resistance TJ = 25 °C, IO = 1 A 165 200 mΩ
TJ = 125 °C, IO = 1 A 250 300 mΩ
TJ = 150 °C, IO = 1 A 280 350 mΩ
tSR Output slew rate VVM = 24 V, IO = 1 A, Between 10% and 90% 240 V/µs
PWM CURRENT CONTROL (VREF)
KV Transimpedance gain VREF = 3.3 V 1.254 1.32 1.386 V/A
IVREF VREF Leakage Current VREF = 3.3 V

8.25

 μA
tOFF PWM off-time TOFF = 0 7 μs
TOFF = 1 16
TOFF = Hi-Z 24
TOFF = 330 kΩ to GND 32
ΔITRIP Current trip accuracy 0.25 A < IO < 0.5 A –12 12 %
0.5 A < IO < 1 A –6

6
1 A < IO < 2.5 A –4

4
IO,CH AOUT and BOUT current matching IO = 2.5 A –2.5 2.5 %
PROTECTION CIRCUITS
VUVLO VM UVLO lockout VM falling, UVLO falling 4.1 4.25 4.35 V
VM rising, UVLO rising 4.2 4.35 4.45
VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 100 mV
VCPUV Charge pump undervoltage VCP falling; CPUV report VVM + 2 V
IOCP Overcurrent protection Current through any FET 4 A
tOCP Overcurrent deglitch time 2 μs
tRETRY Overcurrent retry time 4 ms
tOL Open load detection time 50 ms
IOL Open load current threshold 75 mA
TOTSD Thermal shutdown Die temperature TJ 150 165 180 °C
THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 20 °C