ZHCSJ76A March   2018  – April 2019 DRV8343-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions—DRV8343H
    2.     Pin Functions—DRV8343S
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three Phase Smart Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)
          2. 8.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)
          3. 8.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)
          4. 8.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)
          5. 8.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)
          6. 8.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is 75 kΩ to DVDD)
          7. 8.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is 18 kΩ to DVDD)
          8. 8.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)
        2. 8.3.1.2 Device Interface Modes
          1. 8.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 8.3.1.2.2 Hardware Interface
        3. 8.3.1.3 Gate Driver Voltage Supplies
        4. 8.3.1.4 Smart Gate Drive Architecture
          1. 8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 8.3.1.4.3 Propagation Delay
          4. 8.3.1.4.4 MOSFET VDS Monitors
          5. 8.3.1.4.5 VDRAIN Sense Pin
          6. 8.3.1.4.6 nFAULT Pin
      2. 8.3.2 DVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current Sense Amplifiers
        1. 8.3.4.1 Bidirectional Current Sense Operation
        2. 8.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 8.3.4.3 Amplifier Calibration Modes
        4. 8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 8.3.5 Gate Driver Protective Circuits
        1. 8.3.5.1  VM Supply Undervoltage Lockout (UVLO)
        2. 8.3.5.2  VCP Charge Pump Undervoltage Lockout (CPUV)
        3. 8.3.5.3  MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 8.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 8.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 8.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 8.3.5.4  VSENSE Overcurrent Protection (SEN_OCP)
          1. 8.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 8.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 8.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b)
        5. 8.3.5.5  Gate Driver Fault (GDF)
        6. 8.3.5.6  Thermal Warning (OTW)
        7. 8.3.5.7  Thermal Shutdown (OTSD)
          1. 8.3.5.7.1 Latched Shutdown (OTSD_MODE = 0b)
          2. 8.3.5.7.2 Automatic Recovery (OTSD_MODE = 1b)
        8. 8.3.5.8  Open Load Detection (OLD)
          1. 8.3.5.8.1 Open Load Detection in Passive Mode (OLP)
            1. 8.3.5.8.1.1 OLP Steps
          2. 8.3.5.8.2 Open Load Detection in Active Mode (OLA)
        9. 8.3.5.9  Offline Shorts Diagnostics
          1. 8.3.5.9.1 Offline Short-to-Supply Diagnostic (SHT_BAT)
          2. 8.3.5.9.2 Offline Short-to-Ground Diagnostic (SHT_GND)
        10. 8.3.5.10 Reverse Supply Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 SPI
          1. 8.5.1.1.1 SPI Format
    6. 8.6 Register Maps
      1. 8.6.1 Status Registers
        1. 8.6.1.1 FAULT Status Register (Address = 0x00) [reset = 0x00]
          1. Table 16. FAULT Status Register Field Descriptions
        2. 8.6.1.2 DIAG Status A Register (Address = 0x01) [reset = 0x00]
          1. Table 17. DIAG Status A Register Field Descriptions
        3. 8.6.1.3 DIAG Status B Register (Address = 0x02) [reset = 0x00]
          1. Table 18. DIAG Status B Register Field Descriptions
        4. 8.6.1.4 DIAG Status C Register (address = 0x03) [reset = 0x00]
          1. Table 19. DIAG Status C Register Field Descriptions
      2. 8.6.2 Control Registers
        1. 8.6.2.1  IC1 Control Register (Address = 0x04) [reset = 0x00]
          1. Table 21. IC1 Control Field Descriptions
        2. 8.6.2.2  IC2 Control Register (address = 0x05) [reset = 0x40]
          1. Table 22. IC2 Control Field Descriptions
        3. 8.6.2.3  IC3 Control Register (Address = 0x06) [reset = 0xFF]
          1. Table 23. IC3 Control Field Descriptions
        4. 8.6.2.4  IC4 Control Register (Address = 0x07) [reset = 0xFF]
          1. Table 24. IC4 Control Field Descriptions
        5. 8.6.2.5  IC5 Control Register (Address = 0x08) [reset = 0xFF]
          1. Table 25. IC5 Control Field Descriptions
        6. 8.6.2.6  IC6 Control Register (Address = 0x09) [reset = 0x99]
          1. Table 26. IC6 Control Field Descriptions
        7. 8.6.2.7  IC7 Control Register (Address = 0x0A) [reset = 0x99]
          1. Table 27. IC7 Control Field Descriptions
        8. 8.6.2.8  IC8 Control Register (Address = 0x0B) [reset = 0x99]
          1. Table 28. IC8 Control Field Descriptions
        9. 8.6.2.9  IC9 Control Register (Address = 0x0C) [reset = 0x2F]
          1. Table 29. IC9 Control Field Descriptions
        10. 8.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]
          1. Table 30. IC10 Control Field Descriptions
        11. 8.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]
          1. Table 31. IC11 Control Field Descriptions
        12. 8.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]
          1. Table 32. IC12 Control Field Descriptions
        13. 8.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]
          1. Table 33. IC13 Control Field Descriptions
        14. 8.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]
          1. Table 34. IC14 Control Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External MOSFET Support
            1. 9.2.1.2.1.1 Example
          2. 9.2.1.2.2 IDRIVE Configuration
            1. 9.2.1.2.2.1 Example
          3. 9.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 9.2.1.2.3.1 Example
          4. 9.2.1.2.4 Sense Amplifier Bidirectional Configuration
            1. 9.2.1.2.4.1 Example
          5. 9.2.1.2.5 External Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application With One Sense Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 9.2.2.2.1.1 Example
            2. 9.2.2.2.1.2 Unused pins
          2. 9.2.2.2.2 External Components
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Consideration in Generator Mode
    2. 10.2 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DRV8343H PHP PowerPAD™ Package
48-Pin HTQFP With Exposed Thermal Pad
Top View

Pin Functions—DRV8343H

PIN TYPE(1) DESCRIPTION
NO. NAME
1 CPL PWR Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
2 CPH PWR Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
3 VCP PWR Charge pump output. Connect a bypass capacitor between the VCP and VM pins
4 VM PWR Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors VM and PGND pins
5 VDRAIN I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains
6 GHA O High-side gate driver output. Connect to the gate of the high-side power MOSFET
7 SHA I High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND
8 DLA I Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
9 GLA O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
10 SLA I Low-side source sense input. Connect to the low-side power MOSFET source
11 SPA I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor
12 SNA I Current sense amplifier input. Connect to the low-side of the current shunt resistor
13 SNB I Low-side source sense input. Connect to the low-side power MOSFET source
14 SPB I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor
15 SLB I Low-side source sense input. Connect to the low-side power MOSFET source
16 GLB O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
17 DLB I Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
18 SHB I High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND
19 GHB O High-side gate driver output. Connect to the gate of the high-side power MOSFET
20 GHC O High-side gate driver output. Connect to the gate of the high-side power MOSFET
21 SHC I High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND
22 DLC I Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
23 GLC O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
24 SLC I Low-side source sense input. Connect to the low-side power MOSFET source
25 SPC I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor
26 SNC I Current sense amplifier input. Connect to the low-side of the current shunt resistor
27 SOC O Current sense amplifier output
28 SOB O Current sense amplifier output
29 SOA O Current sense amplifier output
30 VREF PWR Current sense amplifier power supply input and reference. Connect a bypass capacitor between VREF and AGND
31 nFAULT OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor
32 MODE I PWM input mode setting. This pin is a 7-level input pin set by an external resistor
33 IDRIVE I Gate drive output current setting. This pin is a 7-level input pin set by an external resistor
34 VDS I VDS monitor trip point setting. This pin is a 7-level input pin set by an external resistor
35 GAIN I Amplifier gain setting. The pin is a 4-level input pin set by an external resistor
36 ENABLE I Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be used to reset fault conditions
37 CAL I Amplifier calibration input. Set logic high to internally short amplifier inputs
38 AGND PWR Device analog ground. Connect to system ground
39 DVDD PWR 3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally source up to 30 mA.
40 nDIAG I Control pin for open load diagnostic and offline short-to-battery and short-to-ground diagnostic. To enable the diagnostics at device power-up, do not connect this pin (or tie it to ground). To disable the diagnostics, connect this pin to the DVDD pin.
41 INHA I High-side gate driver control input. This pin controls the output of the high-side gate driver
42 INLA I Low-side gate driver control input. This pin controls the output of the low-side gate driver
43 INHB I High-side gate driver control input. This pin controls the output of the high-side gate driver
44 INLB I Low-side gate driver control input. This pin controls the output of the low-side gate driver
45 INHC I High-side gate driver control input. This pin controls the output of the high-side gate driver
46 INLC I Low-side gate driver control input. This pin controls the output of the low-side gate driver
47 PGND PWR Device power ground. Connect to system ground
48 NC NC No connect. Do not connect anything to this pin
— Thermal Pad PWR Must be connected to ground
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
DRV8343S PHP PowerPAD™ Package
48-Pin HTQFP With Exposed Thermal Pad
Top View

Pin Functions—DRV8343S

PIN TYPE(1) DESCRIPTION
NO. NAME
1 CPL PWR Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
2 CPH PWR Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
3 VCP PWR Charge pump output. Connect a bypass capacitor between the VCP and VM pins
4 VM PWR Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors between the VM and PGND pins
5 VDRAIN I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains
6 GHA O High-side gate driver output. Connect to the gate of the high-side power MOSFET
7 SHA I High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND
8 DLA I Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
9 GLA O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
10 SLA I Low-side source sense input. Connect to the low-side power MOSFET source
11 SPA I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor
12 SNA I Current sense amplifier input. Connect to the low-side of the current shunt resistor
13 SNB I Low-side source sense input. Connect to the low-side power MOSFET source
14 SPB I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor
15 SLB I Low-side source sense input. Connect to the low-side power MOSFET source
16 GLB O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
17 DLB I Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
18 SHB I High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND
19 GHB O High-side gate driver output. Connect to the gate of the high-side power MOSFET
20 GHC O High-side gate driver output. Connect to the gate of the high-side power MOSFET
21 SHC I High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND
22 DLC I Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
23 GLC O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
24 SLC I Low-side source sense input. Connect to the low-side power MOSFET source
25 SPC I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor
26 SNC I Current sense amplifier input. Connect to the low-side of the current shunt resistor
27 SOC O Current sense amplifier output
28 SOB O Current sense amplifier output
29 SOA O Current sense amplifier output
30 VREF PWR Current sense amplifier power supply input and reference. Connect a bypass capacitors between VREF and AGND
31 nFAULT OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor
32 SDO PP Serial data output. Data is shifted out on the rising edge of the SCLK pin. VSDO determines logic level on the output
33 SDI I Serial data input. Data is captured on the falling edge of the SCLK pin
34 SCLK I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin
35 nSCS I Serial chip select. A logic low on this pin enables serial interface communication
36 ENABLE I Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be used to reset fault conditions
37 CAL I Amplifier calibration input. Set logic high to internally short amplifier inputs
38 AGND PWR Device analog ground. Connect to system ground
39 DVDD PWR 3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally source up to 30 mA.
40 VSDO PWR Supply pin for SDO output. Connect to 5-V or 3.3-V depending on the desired logic level. Connect a bypass capacitors between VSDO and AGND
41 INHA I High-side gate driver control input. This pin controls the output of the high-side gate driver
42 INLA I Low-side gate driver control input. This pin controls the output of the low-side gate driver
43 INHB I High-side gate driver control input. This pin controls the output of the high-side gate driver
44 INLB I Low-side gate driver control input. This pin controls the output of the low-side gate driver
45 INHC I High-side gate driver control input. This pin controls the output of the high-side gate driver
46 INLC I Low-side gate driver control input. This pin controls the output of the low-side gate driver
47 PGND PWR Device power ground. Connect to system ground
48 NC NC No connect. Do not connect anything to this pin
— Thermal Pad PWR Must be connected to ground
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output, PP = push-pull