ZHCSQ30 December 2022 DRV8317
PRODUCTION DATA
If at any time, input supply voltage on the VM pin rises higher than the VOVP rising threshold, all the integrated FETs are in Hi-Z, FAULT, OVP bits (in DEV_STS register) and VM_OV (in SUP_STS register) are set to 1b and the nFAULT pin is driven low. Normal operation resumes automatically (pre-driver operation and the nFAULT pin is released) once retry time (tRETRY) lapses after VM pin voltage is below the VOVP falling threshold as shown inFigure 8-27. The FAULT, OVP and VM_OV bits stay set to 1b until clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).
Retry time (tRETRY) is set by,
IN DRV8317H, OVP_MODE is set to 01b and FAST_TRETRY is fixed at 5-ms.