ZHCSQ30 December 2022 DRV8317
PRODUCTION DATA
DRV8317 loads the configurable register settings from the OTP on every power-up cycle. If an OTP read fault is encountered while configuring the registers, pre-driver is disabled, FAULT, SYSFLT bits (in DEV_STS register) and OTPLD_ERR bit (in SYSIF_STS register) are set to 1b and nFAULT is driven low. Normal operation resumes (pre-driver, FAULT, SYSFLT, OTPLD_ERR bits set to 0b and nFAULT pin is released) when a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST). It is advisable not to operate DRV8317 by issuing a clear fault command in the event of a OTP read fault since the register settings may be in an unknown state and may lead to unexpected device operation.