Table 1. 6-PWM Mode

Table 2. 3-PWM Mode

Table 3. Gate Driver External Components

7.3.3.1 Power Stage Protection

The DRV8303 provides over-current and undervoltage protection for the MOSFET power stage. During fault shut down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.

7.3.3.2 Overcurrent Protection (OCP) and Reporting

To protect the power stage from damage due to excessive currents, VDS sensing circuitry is implemented in the DRV8303. Based on the R_DS(on) of the external MOSFETs and the maximum allowed IDS, a voltage threshold can be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is programmed through the SPI registers. Overcurrent protection should be used as a protection scheme only; it is not intended as a precise current regulation scheme. There can be up to a 20% tolerance across channels for the VDS trip point.

The V_DS sense circuit measures the voltage from the drain to the source of the external MOSFET while the MOSFET is enabled. The high-side sense is between the PVDD and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provide accurate V_DS sensing .

There are four different overcurrent modes (OC_MODE) that can be set through the SPI registers. The OC status bits operate in latched mode. When an overcurrent condition occurs the corresponding OC status bit will latch in the DRV8303 registers until the fault is reset.

1. Current Limit Mode: In current limit mode the device uses current limiting instead of device shutdown during an overcurrent event. In this mode the device reports overcurrent events through the nOCTW pin. The nOCTW pin will be held low for a maximum 64-µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered from another MOSFET, during a previous overcurrent event, the reporting will continue for another 64-µs period (internal timer will restart) or until both PWM signals cycle. The associated status bit will be asserted for the MOSFET in which the overcurrent was detected. There are two current control settings in current limit mode. These are set by one bit in the SPI registers. The default mode is cycle by cycle (CBC).
   • Cycle-By-Cycle Mode (CBC): In CBC mode, the MOSFET on which overcurrent has been detected on will shut off until the next PWM cycle.
   • Off-Time Control Mode: In Off-Time mode, the MOSFET in which overcurrent has been detected is disabled for a 64-µs period (set by internal timer). If overcurrent is detected in another MOSFET, the timer will be reset for another 64-µs period and both MOSFETs will be disabled for the duration. During this period, normal operation can be restored for a specific MOSFET with a corresponding PWM cycle.
2. OC Latch Shut Down Mode: When an overcurrent event occurs, both the high-side and low-side MOSFETs will be disabled in the corresponding half-bridge. The nFAULT pin, nFAULT status bit, and OC status bit for the MOSFET in which the overcurrent was detected will latch until the fault is reset through the GATE_RESET bit or a quick EN_GATE reset pulse.
3. Report Only Mode: No protective action will be taken in this mode when an overcurrent event occurs. The overcurrent event will be reported through the nOCTW pin (64-µs pulse) and SPI status register. The external MCU should take action based on its own control algorithm.
4. OC Disable Mode: The device will ignore and not report all overcurrent detections.

7.3.3.3 Undervoltage Protection (UVLO)

To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the DRV8303 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDD or GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs in a high impedance state. When the device is in PVDD_UV it will not respond to SPI commands and the SPI registers will revert to their default settings.

A specific PVDD undervoltage transient brownout from 13 to 15 µs can cause the DRV8303 to become unresponsive to external inputs until a full power cycle. The transient condition consists of having PVDD greater than the PVDD_UV level and then PVDD dropping below the PVDD_UV level for a specific period of 13 to 15 µs. Transients shorter or longer than 13 to 15 µs will not affect the normal operation of the undervoltage protection. Additional bulk capacitance can be added to PVDD to reduce undervoltage transients.

7.3.3.4 Overvoltage Protection (GVDD_OV)

The device will shut down both the gate driver and charge pump if the GVDD voltage exceeds the GVDD_OV threshold to prevent potential issues related to the GVDD pin or the charge pump (for example, short of external GVDD cap or charge pump). The fault is a latched fault and can only be reset through a reset transition on the EN_GATE pin.

7.3.3.5 Overtemperature Protection

A two-level over-temperature detection circuit is implemented:

• Level 1: overtemperature warning (OTW)
  OTW is reported through nOCTW pin (over-current-temperature warning) for default setting. OCTW pin can be set to report OTW or OCW only through SPI command. See SPI Register section.
• Level 2: overtemperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)
  Fault will be reported to nFAULT pin. This is a latched shut down, so gate driver will not be recovered automatically even OT condition is not present anymore. An EN_GATE reset through pin or SPI (RESET_GATE) is required to recover gate driver to normal operation after temperature goes below a preset value, t_{OTSD_CLR}.

SPI operation is still available and register settings will be remaining in the device during OTSD operation as long as PVDD is still within defined operation range.

7.3.3.6 Fault and Protection Handling

The nFAULT pin indicates an error event with shut down has occurred such as over-current, over-temperature, overvoltage, or undervoltage. Note that nFAULT is an open-drain signal. nFAULT will go high when gate driver is ready for PWM signal (internal EN_GATE goes high) during start up.

The nOCTW pin indicates overcurrent event and over temperature event that not necessary related to shut down.

Table 4 summarizes all protection features and their reporting structure:

7.5.1.1 SPI

The DRV8303 SPI operates as a slave. The SPI input (SDI) data format consists of a 16 bit word with 1 read/write bit, 4 address bits, and 11 data bits. The SPI output (SDO) data format consists of a 16 bit word with 1 frame fault bit, 4 address bits, and 11 data bits. When a frame is not valid, frame fault bit will set to 1 and the remaining bits will shift out as 0.

A valid frame must meet following conditions:

• Clock must be low when nSCS goes low.
• Should have 16 full clock cycles.
• Clock must be low when nSCS goes high.

When nSCS is asserted high, any signals at the SCLK and SDI pins are ignored and SDO is forced into a high impedance state. When nSCS transitions from HIGH to LOW, SDO is enabled and the SDO response word loads into the shift register based on the previous SPI input word.

The SCLK pin must be low when nSCS transitions low. While nSCS is low, at each rising edge of the clock the response word is serially shifted out on the SDO pin with the MSB shifted out first.

While SCS is low, at each falling edge of the clock the new input word is sampled on the SDI pin. The SPI input word is decoded to determine the register address and access type (read or write). The MSB will be shifted in first. Any amount of time may pass between bits, as long as nSCS stays active low. This allows two 8-bit words to be used. If the input word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error. If it is a write command, the data will be ignored. The fault bit in the next SDO response word will then report 1. After the 16th clock cycle or when nSCS transitions from LOW to HIGH, the SDI shift register data is transferred into a latch where the input word is decoded.

For a READ command (Nth cycle) sent to SDI, SDO will respond with the data at the specified address in the next cycle. (N+1)

For a WRITE command (Nth cycle) sent to SDI, SDO will respond with the data in Status Register 1 (0x00) in the next cycle (N+1). This feature is intended to maximize SPI communication efficiency when having multiple write commands.

7.5.1.2 SPI Format

The SDI input data word is 16 bits long and consists of:

• 1 read/write bit W [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]

The SDO output data word is 16 bits long and consists of:

• 1 fault frame bit F [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]

The SDO output word (Nth cycle) is in response to the previous SDI input word (N-1 cycle).

Therefore each SPI Query/Response pair requires two full 16 bit shift cycles to complete.

Table 7. Register Address

7.6.3.1 Status Registers

7.6.3.2 Control Registers

7.6.3.3 Overcurrent Adjustment