ZHCSE90A September 2015 – October 2015 DLPC910
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DLPC910 controller verifies the DMD connected in the application system, uses that information to select appropriate configuration data for the DMD, and then initializes the DMD to ready it for operation.
The DLPC910 controller receives streaming 64-bit parallel input data and associated syncs from an external applications processor and passes the 64-bit data on to the DLP9000X DMD with the appropriate DMD timing and control information. It also receives embedded instructions from the applications processor to assist in determination of which DMD rows to load and which DMD mirror blocks to activate at any given moment in time.
Direct-write digital imaging is regularly used in high-end lithography printing. This mask-less technology offers continuous run of printing by changing the digitally created patterns without stopping the imaging head. The DLPC910 digital controller, coupled with the DLP9000XFLS DMD, offers an ideal back-end imager that takes in digital images at 2560 × 1600 in resolution to achieve speeds greater than 61 Gigabits per second (Gbps).
As high-end lithography pushes the high speed printing envelope, providing a higher resolution imager is a must to achieve the demanding through-put of present and future printing technology. Figure 14 shows a system that offers both a speed boost and a four million pixel DMD. The main chipset components that make up this system are the DLPC910ZYR, the DLPR910YVA, and the DLP9000XFLS. With a few additional discrete components for power regulation and clock circuitry, a compact, and yet high performance design can be achieved.
The DLPC910 interface is made up of several buses and controls signals as shown in the following list. The LVDS input buses provides the means of loading data to the DLPC910 and the LVDS output buses provide the data to DMD. Each input and output LVDS bus has an associated clock which clocks the data into the DLPC910 or into the DLP9000X. Row and Block control signals define the type of mirror clock pulse to use after all the data is loaded into the DLP9000X.
After power is applied to the DLPC910, the APPS FPGA should monitor the ECP2_FINISHED signal to determine when the DLPC910 has completed loading the configuration from the DLPR910. The APPS FPGA next monitors the INIT_ACTIVE signal to determine when the DLPC910 has completed its internal initialization routines and has configured the DMD for normal operation. An alternate method is to request the initialization status using the I2C interface. Information regarding initialization, versions, and IDs can be requested through this interface.
Prior to activating the DVALID signals to the DLPC910, the ROWMD, ROWAD, BLKMD, BLKAD, and RST2BLKZ control input signals must be in the desired state for the desired operation to take effect on the DLP9000X DMD. Once the control signals are set, the Apps FPGA activates DVALID and starts loading data using the DDC_DIN and DDC_DCLK buses. After all data is loaded for the desired DMD operation, the DVALID signal is de-asserted, and the BLKMD, BLKAD, and RST2BLKZ control signals are set prior to the assertion of the next DVALID. When DVALID is activated, the MCP causes the prior data to take effect on the mirrors of the DMD. The Apps FPGA should then monitor the RST_ACTIVE pin to determine when the mirror clock pulse has completed in order to perform the next MCP. During the time that the RST_ACTIVE is asserted, the Apps FPGA could be loading data into DMD rows that do not belong to the same block of rows that currently has an outstanding MCP.
In this particular application, the performance plot shown in Figure 15 shows the maximum loaded and displayed pixels per second when the exposure period is set to its minimum for the different reset modes. When the exposure period is increased, the pixels per second will decrease. Refer to Mirror Clocking Pulse for more information regarding exposure period.