ZHCSE90A September   2015  – October 2015 DLPC910

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Power Down
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_IRQ
        5. 7.3.7.5 LED Indicators
          1. 7.3.7.5.1 VLED0
          2. 7.3.7.5.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档 
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DLPC910 controller verifies the DMD connected in the application system, uses that information to select appropriate configuration data for the DMD, and then initializes the DMD to ready it for operation.

The DLPC910 controller receives streaming 64-bit parallel input data and associated syncs from an external applications processor and passes the 64-bit data on to the DLP9000X DMD with the appropriate DMD timing and control information. It also receives embedded instructions from the applications processor to assist in determination of which DMD rows to load and which DMD mirror blocks to activate at any given moment in time.

8.2 Typical Application

Direct-write digital imaging is regularly used in high-end lithography printing. This mask-less technology offers continuous run of printing by changing the digitally created patterns without stopping the imaging head. The DLPC910 digital controller, coupled with the DLP9000XFLS DMD, offers an ideal back-end imager that takes in digital images at 2560 × 1600 in resolution to achieve speeds greater than 61 Gigabits per second (Gbps).

8.2.1 High Speed Lithography Application

As high-end lithography pushes the high speed printing envelope, providing a higher resolution imager is a must to achieve the demanding through-put of present and future printing technology. Figure 14 shows a system that offers both a speed boost and a four million pixel DMD. The main chipset components that make up this system are the DLPC910ZYR, the DLPR910YVA, and the DLP9000XFLS. With a few additional discrete components for power regulation and clock circuitry, a compact, and yet high performance design can be achieved.

DLPC910 typ_app_hi_spd_dlps064.gif Figure 14. Typical High Speed Lithography Application

8.2.1.1 Design Requirements

The DLPC910 interface is made up of several buses and controls signals as shown in the following list. The LVDS input buses provides the means of loading data to the DLPC910 and the LVDS output buses provide the data to DMD. Each input and output LVDS bus has an associated clock which clocks the data into the DLPC910 or into the DLP9000X. Row and Block control signals define the type of mirror clock pulse to use after all the data is loaded into the DLP9000X.

  • LVDS differential inputs
    • DDC_DCLK 4 buses
    • DVALID 4 buses
    • DDC_DIN 4 buses
  • LVDS differential outputs. Refer to LVDS Output Bus Skew for recommendations on trace lengths.
    • DDC_DOUT 4 buses
    • DDC_DCLKOUT 4 buses
    • DDC_SCTRL 4 buses
  • Control output signals
    • DMD RESET
    • DMD SCP
  • Row and Block control input signals
    • ROWMD
    • ROWAD
    • BLKMD
    • BLKAD
    • RST2BLKZ
  • Control input signals
    • COMP_DATA
    • NS_FLIP
    • WDT_ENBLZ
    • PWR_FLOAT
    • LOAD4_ENZ
  • Status output signals
    • RST_ACTIVE
    • INIT_ACTIVE
    • ECP2_FINISHED
    • DMD_IRQ
  • Controller reset
    • CTRL_RSTZ
  • DLPR910 interface
    • PGM(4:0)
    • JTAG(3:0)

8.2.1.2 Detailed Design Procedure

After power is applied to the DLPC910, the APPS FPGA should monitor the ECP2_FINISHED signal to determine when the DLPC910 has completed loading the configuration from the DLPR910. The APPS FPGA next monitors the INIT_ACTIVE signal to determine when the DLPC910 has completed its internal initialization routines and has configured the DMD for normal operation. An alternate method is to request the initialization status using the I2C interface. Information regarding initialization, versions, and IDs can be requested through this interface.

Prior to activating the DVALID signals to the DLPC910, the ROWMD, ROWAD, BLKMD, BLKAD, and RST2BLKZ control input signals must be in the desired state for the desired operation to take effect on the DLP9000X DMD. Once the control signals are set, the Apps FPGA activates DVALID and starts loading data using the DDC_DIN and DDC_DCLK buses. After all data is loaded for the desired DMD operation, the DVALID signal is de-asserted, and the BLKMD, BLKAD, and RST2BLKZ control signals are set prior to the assertion of the next DVALID. When DVALID is activated, the MCP causes the prior data to take effect on the mirrors of the DMD. The Apps FPGA should then monitor the RST_ACTIVE pin to determine when the mirror clock pulse has completed in order to perform the next MCP. During the time that the RST_ACTIVE is asserted, the Apps FPGA could be loading data into DMD rows that do not belong to the same block of rows that currently has an outstanding MCP.

8.2.1.3 Application Curves

In this particular application, the performance plot shown in Figure 15 shows the maximum loaded and displayed pixels per second when the exposure period is set to its minimum for the different reset modes. When the exposure period is increased, the pixels per second will decrease. Refer to Mirror Clocking Pulse for more information regarding exposure period.

DLPC910 Performance_PlotC_dlps064.gif Figure 15. Performance Plot at 480 MHz DDC_DCLK