ZHCSE90A September   2015  – October 2015 DLPC910

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Power Down
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_IRQ
        5. 7.3.7.5 LED Indicators
          1. 7.3.7.5.1 VLED0
          2. 7.3.7.5.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档 
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
ELECTRICAL
VCCINT Supply voltage range (2) –0.50 1.1 V
VCCO –0.50 3.75
VCCAUX –0.50 3.0
VI Input voltage range (3) 3.3 V –0.95 4.05 V
2.5 V –0.75 VCCO + 0.50
VO Output voltage range (4) 3.3 V –0.30 VCCO – 0.40 V
2.5 V –0.30 VCCO – 0.40
ENVIRONMENTAL
TJ Junction temperature 125 °C
Tstg Storage temperature (ambient) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Applies to external input and bidirectional buffers.
(4) Applies to external output and bidirectional buffers.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ± 2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ± 1500
(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
ELECTRICAL
VCCINT 1-V supply voltage, core logic 0.95 1.00 1.05 V
VCCO 2.5-V supply voltage, I/O for VCCO_1,3,11,12,13,14,15,16,17,18,21 1.14 2.50 3.45 V
VCCO 3.3-V supply voltage, I/O for VCCO_0,2,4 3.0 3.30 3.45 V
VCCAUX 2.5-V supply voltage, I/O 2.375 2.500 2.625 V
VI Input voltage 3.3-V DCI and CMOS for VCCO_0,2,4 0 VCCO V
2. 5-V CMOS for VCCO_1,3,11,12,13,14,15,16,17,18,21 0 VCCO
2.5-V LVDS 0.3 2.2
VO Output voltage 3.3-V DCI and CMOS for VCCO_0,2,4 0 VCCO V
2.5-V CMOS for VCCO_1,3,11,12,13,14,15,16,17,18,21 0 VCCO
2.5-V LVDS 0.825 1.675
TA Operating ambient temperature 0 85 °C
ENVIRONMENTAL
PD Continuous total power dissipation 6 W

6.4 Thermal Information

THERMAL METRIC (1) DLPC910 UNIT
ZYR (FCBGA)
676 PINS
RθJA Junction-to-ambient thermal resistance (2) 12.1 °C/W
RθJC Junction-to-case thermal resistance 3.2 °C/W
RθJB Junction-to-board thermal resistance 0.19 °C/W
(1) Refer to the XC5VLX30 product specifications at www.xilinx.com for complete thermal specifications.
(2) In still air.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
VIH High-level input voltage 3.3-V CMOS 2.0 V
VIL Low-level input voltage 3.3-V CMOS 0.8 V
VOH High-level output voltage 3.3-V DCI and CMOS 2.9 V
VOL Low-level output voltage 3.3-V DCI and CMOS 0.4 V
VIH High-level input voltage 2.5-V CMOS 1.7 V
VIL Low-level input voltage 2.5-V CMOS 0.7 V
VOH High-level output voltage 2.5-V interface VCCO – 0.4 V
2.5-V LVDS 1.38
VOL Low-level output voltage 2.5-V interface 0.4 V
2.5-V LVDS 1.03
CI Input capacitance 2.5-V interface 8 pF
2.5-V LVDS 8
ICCINT Supply voltage range, core supply 1.4 mA
ICCO Supply voltage range, I/O supply 4.2 mA

6.6 Timing Requirements

(see (1))
MIN NOM MAX UNIT
fcd Clock frequency, DCLKIN_n (2) fcd = 400 MHz 400 MHz
fcd = 480 MHz 480
fcr Clock frequency, CLK_R 50 MHz
tc Cycle time, DCLKIN_n fcd = 400 MHz 2.5 ns
fcd = 480 MHz 2.083
tw(H) Pulse duration, high 50% to 50% reference points (signal) fcd = 400 MHz 1.25 ns
fcd = 480 MHz 1.042
tw(L) Pulse duration, low 50% to 50% reference points (signal) fcd = 400 MHz 1.25 ns
fcd = 480 MHz 1.042
tt Transition time, tt = tf /tr 20% to 80% reference points (signal) fcd = 400 MHz 0.6 ns
fcd = 480 MHz 0.5
tjp Period Jitter DCLKIN_n (3) 100 ps
tsk Skew, DIN_A(15-0) to DCLKIN_A -100 100 ps
Skew, DIN_B(15-0) to DCLKIN_B -100 100
Skew, DIN_C(15-0) to DCLKIN_C -100 100
Skew, DIN_D(15-0) to DCLKIN_D -100 100
Skew, DVALID_n to DCLKIN_n↑ -100 100
Skew, BLK_MD BLK_AD to DCLKIN_n↑ (4) -100 100
Skew, ROWMD or ROWAD to DCLKIN_n↑ (4) -100 100
Skew, STEPVCC to DCLKIN↑ (4) -100 100
(1) It is recommended that the COMP_DATA, NS_FLIP and RST2BLKZ flags be set to one value and not adjusted during normal system operation.
(2) Preferred DDC_DCLK _n duty cycle = 50%
(3) This is the deviation in period from ideal period due solely to high frequency jitter.
(4) First edge of DDC_DIN*, ROW*, and BLK* should be synchronous to DVALID rising edge.
DLPC910 ip_iface_tim_lps024.gif Figure 1. Input Interface Timing
DLPC910 td_02_control_timing_dlps064.gif Figure 2. Control Timing