ZHCSE90A September 2015 – October 2015 DLPC910
PRODUCTION DATA.
One of the most important factors to gain good performance is designing the PCB with the highest quality signal integrity possible. The following PCB design guidelines provide a reference of an interconnect system..
PCBs should be designed and built in accordance with the industry specifications shown in Table 19.
INDUSTRY SPECIFICATION | APPLICABLE TO |
---|---|
IPC-2221 and IPC2222, Type 3, Class X, at Level B producibility | Board design |
IPC-6011 and IPC-6012, Class 2 | PWB fabrication |
IPC-SM-840, Class 3, Color Green | Finished PWB solder mask |
UL94V-0 Flammability Rating and Marking | Finished PWB |
UL796 Rating and Marking | Finished PWB |
PCB Fabrication:
PCB Stack-up:
The PCB signal layers should follow typical good practice guidelines including:
The PCB should have a solder mask on the top and bottom layers.
High-speed connectors that meet the following requirements should be used:
Routing requirements for right-angle connectors:
Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.
BGA escape routing can be routed with 3.7-mils width and 4.3-mils spacing, as long as the escape nets are less than 1-inch long, to allow two traces to fit between vias. After signals escape the BGA field, trace width should be widened to achieve the desired impedance and spacing.
All single-ended 50-ohm signals must have a minimum spacing of 10 mils relative to other signals. Other special trace spacing requirements are listed in Table 20.
SIGNAL | PWR | GND | SINGLE-ENDED (1) | DIFFERENTIAL PAIRS | UNIT |
---|---|---|---|---|---|
Pair-to-Pair (2) | |||||
PWR | 20 (3) | 10 | 15 | 15 | mils |
GND | 10 | 5 | 5 | mils | |
CLKIN_R | 15 | 5 | 30 | 30 | mils |
DDC_DCLK_[A,B,C,D]_DP[N,P] | 15 | 5 | 30 | 30 | mils |
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] | 15 | 5 | 30 | 30 | mils |
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] | 15 | 5 | 30 | 30 | mils |
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] | 15 | 5 | 30 | 30 | mils |
DDC_SCTRL_[A,B,C,D][N,P] | 15 | 5 | 30 | 30 | mils |
DVALID_[A,B,C,D]_DP[N,P] | 15 | 5 | 30 | 30 | mils |
Escape routing in ball field | 15 | 5 | 4.3 | 4.3 | mils |
All other signals | 15 | 5 | 30 | 30 | mils |
SIGNAL | MIN WIDTHS | MAX LENGTHS (2) | MAXIMUM TRACE MISMATCH | UNIT | |
---|---|---|---|---|---|
N-to-P | Pair-to-pair | ||||
PWR | 25 | mils | |||
GND | 15 (1) | mils | |||
CLKIN_R | 7 | 350 | mils | ||
DDC_DCLK_[A,B,C,D]_DP[N,P] | Layout specific (4) | Layout specific (5) | 10 | mils | |
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] | 10 | 50 (3) | mils | ||
DVALID_[A,B,C,D]_DP[N,P] | 10 | 50 (3) | mils | ||
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] | 10 | mils | |||
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] | 10 | 50 (3) | mils | ||
DDC_SCTRL_[A,B,C,D][N,P] | 10 | 50 (3) | mils | ||
All other signals | 7 | mils |
To minimize instantaneous AC current switching in the DMD, the LVDS output bus trace lengths should differ to produce a recommneded 100-200 ps skew from one bus to another. Table 22 shows two examples how buses can be skewed assuming 180-200 ps per 1000 mils. Keep in mind the total skew from one bus to another should be kept below the maximum skew for the DMD. Refer to 相关文档 for the DMD datasheet regarding maximum DMD LVDS input bus skew.
Bus Group | Example 1 Bus Group Trace Lengths |
Example 2 Bus Group Trace Lengths |
UNIT |
---|---|---|---|
DDC_DCLKOUT_A DDC_DOUT_A DDC_SCTRL_A |
7454 | 7454 | mils |
DDC_DCLKOUT_B DDC_DOUT_B DDC_SCTRL_B |
5257 | 7454 | mils |
DDC_DCLKOUT_C DDC_DOUT_C DDC_SCTRL_C |
6936 | 5257 | mils |
DDC_DCLKOUT_D DDC_DOUT_D DDC_SCTRL_D |
5886 | 5257 | mils |
For best performance, it is recommended that the trace impedance for differential signals as in Table 23.
All signals should be 50-ohms controlled impedance unless otherwise noted in Table 23.
SIGNALS | DIFFERENTIAL IMPEDANCE |
---|---|
DDC_DCLK_[A,B,C,D]_DP[N,P] | 100 Ω ± 10% |
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] | 100 Ω ± 10% |
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] | 100 Ω ± 10% |
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] | 100 Ω ± 10% |
DDC_SCTRL_[A,B,C,D][N,P] | 100 Ω ± 10% |
DVALID_[A,B,C,D]_DP[N,P] | 100 Ω ± 10% |
Table 24 lists the routing priority and layer assignments of the signals.
SIGNALS | Priority |
---|---|
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] | 1 |
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] | 1 |
DDC_SCTRL_[A,B,C,D][N,P] | 2 |
DDC_DCLK_[A,B,C,D]_DP[N,P] | 2 |
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] | 3 |
DVALID_[A,B,C,D]_DP[N,P] | 3 |
BLKAD_[0:3], BLKMD_[0:1], ROWAD_[0:10], ROWMD_[0:1] | 4 |
RESET_ADDR[0:3], RESET_MODE[0:1], RESET_SEL[0:1], RESET_STROBE, RESET_OEZ, RESET_IRQZ, RESET_RSTZ |
5 |
SCPCLK, SCPDI, SCPDO, DMD_SCPENZ | 6 |
CLKIN_R | 7 |
All other single-ended signals | 8 |
The following are recommendations for best performance:
Power and Ground pins of each component shall be connected to the power and ground planes with a via for each pin. Avoid sharing vias to the power plane among multiple power pins, where possible. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100 inch). Unused or spare device pins that are connected to power or ground may be connected together with a single via to power or ground. The minimum spacing between vias shall be 0.050 inch to prevent slots from being developed on the ground plane.
Decoupling capacitors must be located as near as possible to the DLPC910 voltage supply pins. Capacitors should not share vias. The DLPC910 power pins can be connected directly to the decoupling capacitor (no via) if the trace is less than 0.03 inches. Otherwise the component should be tied to the voltage or ground plane through a separate via. All capacitors should be connected to the power planes with trace lengths less than 0.05 inches.
For designs using the Texas Instruments designed reference flex cable, plate all the pad area on the top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of electrolytic hard gold over a minimum of 100 micro-inches of electrolytic nickel.
The PCB layer design may vary depending on system design. However, careful attention is required to meet design considerations. Table 25 shows a layer signal definition and Figure 17 shows a PCB stack-up. The PCB stack-up uses Hitachi 679gs as the dielectric material to improve the signal slew rate. Although the material shown is Rogers Theta, it is the same material as the Hitachi 679gs.
Top: | Signal |
---|---|
2: | GND |
3: | Signal |
4: | GND |
5: | Signal |
6: | GND |
7: | Signal |
8: | GND |
9: | Split Power |
10: | Split Power |
11: | GND |
12: | Signal |
13: | GND |
14: | Signal |
15: | GND |
16: | Signal |
17: | GND |
Bottom: | Signal |