ZHCSE90A September   2015  – October 2015 DLPC910

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Power Down
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_IRQ
        5. 7.3.7.5 LED Indicators
          1. 7.3.7.5.1 VLED0
          2. 7.3.7.5.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档 
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

One of the most important factors to gain good performance is designing the PCB with the highest quality signal integrity possible. The following PCB design guidelines provide a reference of an interconnect system..

10.1.1 PCB Design Standards

PCBs should be designed and built in accordance with the industry specifications shown in Table 19.

Table 19. Industry Design Specifications

INDUSTRY SPECIFICATION APPLICABLE TO
IPC-2221 and IPC2222, Type 3, Class X, at Level B producibility Board design
IPC-6011 and IPC-6012, Class 2 PWB fabrication
IPC-SM-840, Class 3, Color Green Finished PWB solder mask
UL94V-0 Flammability Rating and Marking Finished PWB
UL796 Rating and Marking Finished PWB

PCB Fabrication:

  • Configuration: Asymmetric dual strip-line
  • Etch thickness : 1.0-oz copper (1.2 mil)
  • Flex etch thickness: 0.5-oz copper (0.6 mil)
  • Single-ended signal impedance: 50 Ω (±10%)
  • Differential signal impedance: 100 Ω (±10%)

PCB Stack-up:

  • Ground planes for proper return path.
  • Power planes for proper supply to circuits.
  • Dielectric material with a low Loss-Tangent, for example: Hitachi 679gs or equivalent, (Er): 3.8 (nominal).

10.1.2 Signal Layers

The PCB signal layers should follow typical good practice guidelines including:

  • Layer changes should be minimized for single-ended signals.
  • Individual differential pairs can be routed on different layers, but the signals of a given pair should not change layers.
  • Stubs should be avoided.
  • Low-frequency signals should be routed on the outer layers.
  • Differential pair signals should be routed first.
  • Pin swapping on components is not allowed.
  • Polarized capacitors should have the same orientation.

The PCB should have a solder mask on the top and bottom layers.

  • The mask should not cover the vias.
  • Except for fine pitch devices (pitch ≤ 0.032 inches). The copper pads and the solder mask cutout should be of the same size.
  • Solder mask between pads of fine pitch devices should be removed.
  • In the BGA package, the copper pads and the solder mask cutout should be of the same size.

High-speed connectors that meet the following requirements should be used:

  • Differential crosstalk: < 5%
  • Differential impedance: 90 to 110 Ω for all LVDS signal pairs

Routing requirements for right-angle connectors:

  • When using right-angle connectors, LVDS signal P-N pairs should be routed in the same row to minimize delay mismatch.
  • When using right-angle connectors, propagation delay difference for each row should be accounted for on associated PCB etch lengths.

10.1.3 General PCB Routing

Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.

10.1.3.1 Trace Minimum Spacing

BGA escape routing can be routed with 3.7-mils width and 4.3-mils spacing, as long as the escape nets are less than 1-inch long, to allow two traces to fit between vias. After signals escape the BGA field, trace width should be widened to achieve the desired impedance and spacing.

All single-ended 50-ohm signals must have a minimum spacing of 10 mils relative to other signals. Other special trace spacing requirements are listed in Table 20.

Table 20. Trace Minimum Spending

SIGNAL PWR GND SINGLE-ENDED (1) DIFFERENTIAL PAIRS UNIT
Pair-to-Pair (2)
PWR 20 (3) 10 15 15 mils
GND 10 5 5 mils
CLKIN_R 15 5 30 30 mils
DDC_DCLK_[A,B,C,D]_DP[N,P] 15 5 30 30 mils
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] 15 5 30 30 mils
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] 15 5 30 30 mils
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] 15 5 30 30 mils
DDC_SCTRL_[A,B,C,D][N,P] 15 5 30 30 mils
DVALID_[A,B,C,D]_DP[N,P] 15 5 30 30 mils
Escape routing in ball field 15 5 4.3 4.3 mils
All other signals 15 5 30 30 mils
(1) Signal spacing relative to other single-end signals.
(2) Signal spacing relative to other differential pairs.
(3) PWR relative to other power sources. Not same power source.

10.1.3.2 Trace Widths and Lengths

Table 21. Trace Widths and Lengths

SIGNAL MIN WIDTHS MAX LENGTHS (2) MAXIMUM TRACE MISMATCH UNIT
N-to-P Pair-to-pair
PWR 25 mils
GND 15 (1) mils
CLKIN_R 7 350 mils
DDC_DCLK_[A,B,C,D]_DP[N,P] Layout specific (4) Layout specific (5) 10 mils
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] 10 50 (3) mils
DVALID_[A,B,C,D]_DP[N,P] 10 50 (3) mils
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] 10 mils
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] 10 50 (3) mils
DDC_SCTRL_[A,B,C,D][N,P] 10 50 (3) mils
All other signals 7 mils
(1) Make width of GND trace as wide as the pin it is connected to, when possible.
(2) Signal routing length includes escape routing.
(3) Relative to its clock system. Refer to to identify the clock system associated with the signals.
(4) Minimum widths to achieve impedance matching.
(5) Keep lengths as short as possible.

10.1.3.2.1 LVDS Output Bus Skew

To minimize instantaneous AC current switching in the DMD, the LVDS output bus trace lengths should differ to produce a recommneded 100-200 ps skew from one bus to another. Table 22 shows two examples how buses can be skewed assuming 180-200 ps per 1000 mils. Keep in mind the total skew from one bus to another should be kept below the maximum skew for the DMD. Refer to 相关文档  for the DMD datasheet regarding maximum DMD LVDS input bus skew.

Table 22. Example LVDS Output Bus Skew

Bus Group Example 1
Bus Group Trace Lengths
Example 2
Bus Group Trace Lengths
UNIT
DDC_DCLKOUT_A
DDC_DOUT_A
DDC_SCTRL_A
7454 7454 mils
DDC_DCLKOUT_B
DDC_DOUT_B
DDC_SCTRL_B
5257 7454 mils
DDC_DCLKOUT_C
DDC_DOUT_C
DDC_SCTRL_C
6936 5257 mils
DDC_DCLKOUT_D
DDC_DOUT_D
DDC_SCTRL_D
5886 5257 mils

10.1.3.3 Trace Impedance and Routing Priority

For best performance, it is recommended that the trace impedance for differential signals as in Table 23.

All signals should be 50-ohms controlled impedance unless otherwise noted in Table 23.

Table 23. Trace Impedance

SIGNALS DIFFERENTIAL IMPEDANCE
DDC_DCLK_[A,B,C,D]_DP[N,P] 100 Ω ± 10%
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] 100 Ω ± 10%
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] 100 Ω ± 10%
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] 100 Ω ± 10%
DDC_SCTRL_[A,B,C,D][N,P] 100 Ω ± 10%
DVALID_[A,B,C,D]_DP[N,P] 100 Ω ± 10%

Table 24 lists the routing priority and layer assignments of the signals.

Table 24. Routing Priority

SIGNALS Priority
DDC_DCLKOUT_[A,B,C,D]_DP[N,P] 1
DDC_DOUT_[A,B,C,D][0:15]_DP[N,P] 1
DDC_SCTRL_[A,B,C,D][N,P] 2
DDC_DCLK_[A,B,C,D]_DP[N,P] 2
DDC_DIN_[A,B,C,D][0:15]_DP[N,P] 3
DVALID_[A,B,C,D]_DP[N,P] 3
BLKAD_[0:3], BLKMD_[0:1], ROWAD_[0:10], ROWMD_[0:1] 4
RESET_ADDR[0:3], RESET_MODE[0:1], RESET_SEL[0:1],
RESET_STROBE, RESET_OEZ, RESET_IRQZ, RESET_RSTZ
5
SCPCLK, SCPDI, SCPDO, DMD_SCPENZ 6
CLKIN_R 7
All other single-ended signals 8

10.1.4 Power and Ground Planes

The following are recommendations for best performance:

  • Solid ground planes between each signal routing layer.
  • Solid power planes for voltages.
  • Power and ground pins should be connected to these planes through a via for each pin.
  • Trace lengths for the component power and ground pins should be minimized to 0.100 inches or less.
  • Vias should be spaced out to avoid forming slots on the power planes.
  • High speed signals should not cross over a slot in the adjacent power planes.
  • Placing extra vias is not required if there are sufficient ground vias due to normal ground connections of devices.

10.1.5 Power Vias

Power and Ground pins of each component shall be connected to the power and ground planes with a via for each pin. Avoid sharing vias to the power plane among multiple power pins, where possible. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100 inch). Unused or spare device pins that are connected to power or ground may be connected together with a single via to power or ground. The minimum spacing between vias shall be 0.050 inch to prevent slots from being developed on the ground plane.

10.1.6 Decoupling

Decoupling capacitors must be located as near as possible to the DLPC910 voltage supply pins. Capacitors should not share vias. The DLPC910 power pins can be connected directly to the decoupling capacitor (no via) if the trace is less than 0.03 inches. Otherwise the component should be tied to the voltage or ground plane through a separate via. All capacitors should be connected to the power planes with trace lengths less than 0.05 inches.

10.1.7 Flex Connector Plating

For designs using the Texas Instruments designed reference flex cable, plate all the pad area on the top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of electrolytic hard gold over a minimum of 100 micro-inches of electrolytic nickel.

10.2 Layout Example

The PCB layer design may vary depending on system design. However, careful attention is required to meet design considerations. Table 25 shows a layer signal definition and Figure 17 shows a PCB stack-up. The PCB stack-up uses Hitachi 679gs as the dielectric material to improve the signal slew rate. Although the material shown is Rogers Theta, it is the same material as the Hitachi 679gs.

Table 25. Layer Definition

Top: Signal
2: GND
3: Signal
4: GND
5: Signal
6: GND
7: Signal
8: GND
9: Split Power
10: Split Power
11: GND
12: Signal
13: GND
14: Signal
15: GND
16: Signal
17: GND
Bottom: Signal
DLPC910 pcb_stackup_dlps064.gif Figure 17. PCB Stack-Up